Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-04-25
2006-04-25
Padmanabhan, Mano (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S118000, C711S127000, C711S157000, C711S207000
Reexamination Certificate
active
07035986
ABSTRACT:
An embodiment of the invention is a processor for providing simultaneous access to the same data for a plurality of requests. The processor includes cache storage having an address sliced directory lookup structure. A same line detection unit receives a plurality of first instruction fields and a plurality of second instruction fields. The same line detection unit generates a same line signal in response to the first instruction fields and the second instruction fields. The cache storage simultaneously reads data from a single line in the cache storage in response to the same line signal.
REFERENCES:
patent: 5640534 (1997-06-01), Liu et al.
patent: 5805855 (1998-09-01), Liu
patent: 5890217 (1999-03-01), Kabemoto et al.
patent: 6202128 (2001-03-01), Chan et al.
patent: 6493800 (2002-12-01), Blumrich
Check Mark A.
Navarro Jennifer A.
Shum Chung-Lung K.
Slegel Timothy J.
Tsai Aaron
Augspurger Lynn L.
Cantor & Colburn LLP
International Business Machines - Corporation
Namazi Mehdi
Padmanabhan Mano
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