Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-24
2003-10-28
Loke, Steven (Department: 2811)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06640330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly, to systems and methods for enhancing setup and hold characterization in an integrated circuit.
2. Description of the Related Art
Generally, semiconductor integrated circuits are designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to form a particular logical function. With standard cell technology, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library.
FIG. 1
is a schematic diagram of a section of an exemplary prior art integrated circuit
100
. The integrated circuit section
100
includes a plurality of rows
102
separated into standard cells
104
. Each standard cell
104
corresponds to a logical function unit, which is implemented by one or more transistors that are optimized for the cell. These functional units can be combinational cells, such as adders and gates, or sequential cells, such as flip-flops and latches.
Each of the sequential cells has “setup” and “hold” timing constraints, which are recorded in the timing library. During the design process, a series of computer-aided design tools generate a netlist of the selected cells
104
and the interconnections between the cells
104
. A floor planner or placement tool uses the netlist to place the selected cells
104
at particular locations in an integrated circuit layout pattern. The interconnections between the cells
104
are then routed along predetermined routing layers. Once the selected cells
104
have been placed and routed, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition, which is used to fabricate the integrated circuit.
As mentioned above, each of the sequential cells has “setup” and “hold” timing constraints, which are recorded in the timing library. These constraints guide the chip design tool to meet timing goals set during the chip design phase.
FIG. 2
is a schematic diagram showing a prior art flip-flop
200
. The flip-flop
200
includes a data pin
202
, an output pin
204
, and a clock
206
. To ensure the flip-flop
200
is functional, a time constraint exists between the constraint pin, which is the data pin
202
, and the reference pin, which is the clock
206
. For the flip-flop
200
, the data should arrive on the data pin
202
a particular amount of time before the clock
206
is asserted. This time period is referred to as the setup time. Also to ensure the flip-flop
200
is functional, another time constraint exists between the constraint pin
202
and the reference pin
206
. In this case, the data needs to stay on the data pin
202
while the clock
206
is asserted for particular amount of time. This time period is referred to as the hold time.
FIG. 3
is a timing diagram illustrating setup and hold times for the flip-flop
200
. Graph
202
a
illustrates the graph of the data pin
202
and graph
206
a
illustrates a graph of the clock
206
. Point
302
is the time when the data is considered to be stable on the data pin
202
. Point
306
is the time when the clock
206
is considered asserted, and point
304
is the time when the data pin
202
is considered changed.
The time period between point
302
and point
306
is the setup time, which is the minimum amount of the time that the data should be on the data pin
202
before the clock
206
is asserted on the flip-flop
200
. The time period between point
306
and point
304
is the hold time, which is the minimum amount of time that the data should be on the data pin
202
while the clock
206
is asserted on the flip-flop
200
.
Two prior art methods are currently used to determine the setup time and the hold time for standard cells, 1) a test point method and 2) a binary search method. The test point method defines a plurality of test points throughout the cell logic. Next, propagation delays are determined from the input pins to the test points defined in the circuit. The propagation delays are then used to calculate the setup time and hold time constraints for the circuit. Unfortunately, the test point method is not accurate, and therefore, designers are forced to use pessimistic results for the setup and hold time values to ensure operability of the circuit.
The binary search method is an optimization process that runs multiple SPICE simulations with predefined objective (generally propagation delay) to determine setup and hold timing constraints. Since executing multiple SPICE simulations is a slow time consuming process, each of these optimization runs takes long time to complete. The binary search method is further slowed for cells that have more than one “constraint” pin as the optimization runs needs to be executed for each constraint pin and for all the sensitizing states on other constraint pins.
In total, four optimization runs would need to be executed to determine the setup rising time, setup falling time, hold rising time, and hold falling time for the constraint pin
202
and reference pin
206
of the flip-flop
200
of
FIG. 2
using the binary search method. Each sequential cell generally includes a primitive sequential element, such as a flip-flop or latch, and combinational logic that connects the constraint ports of the sequential cell to the constraint port of the primitive sequential element. Further, the reference port of the sequential cell generally is connected to the reference port of the primitive sequential element.
FIG. 4
is a schematic diagram showing a prior art generic sequential cell
400
. The generic sequential cell
400
includes a primitive sequential element
402
and a combinational logic block
404
. The combinational logic block
404
includes three constraint pins S, D
0
, and D
1
. To complete setup and hold characterization of the generic sequential cell
400
, the following timing constraints need to be optimized using binary search method:
setup time when pin D
0
is rising;
setup time when pin D
0
is falling;
hold time when pin D
0
is rising;
hold time when pin D
0
is falling;
setup time when pin D
1
is rising;
setup time when pin D
1
is falling;
hold time when pin D
1
is rising;
hold time when pin D
1
is falling;
setup time when pin S is rising and D
0
=1, D
1
=0;
setup time when pin S is falling and D
0
=1, D
1
=0;
hold time when pin S is rising and D
0
=1, D
1
=0;
hold time when pin S is falling and D
0
=1, D
1
=0;
setup time when pin S is rising and D
0
=0, D
1
=1;
setup time when pin S is falling and D
0
=0, D
1
=1;
hold time when pin S is rising and D
0
=0, D
1
=1;
hold time when pin S is falling and D
0
=0, D
1
=1;
Thus, the number of optimization runs increases from four to sixteen when the combinational logic block
404
is added to the primitive sequential element
402
. Moreover, the number of optimization runs increases further when more complex combinational logic is used in a sequential cell, resulting in slower setup and hold characterization.
In view of the foregoing, there is a need for systems and methods that provide enhanced setup and hold characterization. The methods should be capable of providing fast setup and hold characterization, while being accurate in determining values for the setup and hold times of a standard cell.
SUMMARY OF THE INVENTION
Broadly speaking, the present invention fills these needs by providing a method for accurately characterizing the constraint pins of an integrated circuit cell. The method provides accuracy comparable to a binary search pin characterization method, while increasing the speed with which the characterization can be performed. In one embodiment, a method for setup and hold characterization in an integrated circuit cell is disclosed. The method includes obtaining a setup time for a fi
Artisan Components Inc.
Loke Steven
Martine & Penilla LLP
Owens Douglas W.
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