System and method for setting and executing breakpoints

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C714S035000, C714S038110, C717S129000

Reexamination Certificate

active

06862694

ABSTRACT:
A system and method for setting and executing breakpoints utilized for debugging program code. A user interface (UI) stores breakpoint addresses in a breakpoint table within a central processing unit (CPU). Multiple breakpoint addresses may be stored in the table as a range of addresses in a single entry. A flag indicates whether each stored address or address range is a physical or virtual address. When executing the program code on the CPU, an instruction core requests from an instruction cache, an instruction associated with a particular address. The cache first determines from the breakpoint table within the CPU whether there is a breakpoint associated with the particular address. If so, the cache returns control to the UI. Otherwise, the cache goes out to a coherency controller to fetch the instruction from memory.

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patent: 5664159 (1997-09-01), Richter et al.
patent: 5812850 (1998-09-01), Wimble
patent: 6052801 (2000-04-01), Hammond et al.
patent: 6493806 (2002-12-01), Royer et al.

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