Electrical computers and digital data processing systems: input/ – Interrupt processing – Interrupt inhibiting or masking
Reexamination Certificate
1999-01-06
2001-07-17
Myers, Paul R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Interrupt processing
Interrupt inhibiting or masking
C710S049000, C710S120000
Reexamination Certificate
active
06263395
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This disclosure relates to interrupts within a computer system and, more particularly, to serially scanning interrupt signals and avoiding associated spurious interrupts in a computer system
2. Description of the Related Art
A typical computer system contains at least one interrupt service provider, usually a central processing unit (CPU), and a number of input/output (I/O) devices peripheral to the CPU(s). These I/O devices commonly include hard disk drives, optical disk drives, video adapters, parallel ports, serial ports, and other similar I/O type devices. An I/O device may need to alert the CPU(s) or request service when it completes a task or has a status change, such as finishing a data transfer, completing an operation, receiving data, or the occurrence of an error condition.
The typical mechanism for an I/O device to request service from the CPU(s) involves an interrupt request. An interrupt request is generally a hardware signal sent from the requesting device to an interrupt controller to notify a CPU that the I/O device requires service. Other system devices such as timers, direct memory access (DMA) controllers, and other processors may generate interrupt request signals.
One advantage of using interrupts over other techniques, such as polling, is that the CPU is free to perform other operations between interrupts. When a CPU receives an interrupt request, it stops executing the current instruction routine, saves its state, and jumps to an interrupt service routine. The interrupt service routine includes instructions specific to the device requesting the interrupt so that the CPU can respond to the device condition or status change that instigated the interrupt request. When the interrupt service routine is completed, the CPU restores its state and returns to its location prior to the interrupt.
Generally speaking, in a typical system, a programmable interrupt controller receives the interrupt request signals from the various system devices and organizes the requests to be sent to the CPU(s). A typical interrupt controller has a separate input conductor for each interrupt request signal. In PCs, the so called “legacy interrupts” are usually supported in an interrupt controller. Two cascaded 8259-type interrupt controllers may receive the “legacy” interrupt request signals IRQ[
15
:
3
,
1
]. Historically, IRQ
2
has been used for cascading the 8259 interrupt controllers and IRQ
0
is often implemented as an internal timer interrupt. In more modern systems, the interrupt controller may receive additional interrupts, such as interrupts from a peripheral component interconnect (PCI) bus or system management interrupts. These additional interrupts add additional input conductors to the interrupt controller. In some cases, a custom interrupt controller may have to be designed to handle the additional interrupts. Usually a larger package size will be required for the additional input conductors. To avoid the need for additional input conductors, interrupt requests may share a single input conductor by wired-OR sharing. However, with wired-OR sharing, the interrupt controller cannot determine the source of the interrupt request. Typically, all devices sharing an interrupt input conductor must be polled to determine which device requested the interrupt. Polling may have a detrimental effect on performance.
SUMMARY OF THE INVENTION
An interrupt controller may be provided for receiving a plurality of different interrupt requests on a single input conductor by serially scanning the plurality of interrupt requests. Interrupt requests may be latched external to the interrupt controller and then serially shifted into the interrupt controller. The interrupts may then be mapped to the appropriate 8259 and/or I/O APIC interrupt requests. Serially scanning multiple interrupt request signals into a single serial input effectively increases the interrupt I/O capacity and resolution as compared to receiving all interrupt requests in parallel on dedicated inputs or wired-OR sharing of interrupt request on an input. The interrupt controller may also receive interrupt request on dedicated inputs in parallel to the interrupt requests received serially. Also, more than one serial interrupt scan input may be provided on the interrupt controller so that, for example, two serial streams of interrupt requests may be received in parallel into the interrupt controller in addition to possibly receiving dedicated single interrupt request inputs in parallel to the serial scan inputs.
Interrupt requests that are serially scanned into the interrupt controller have an added latency associated with the input operation. This latency corresponds to the amount of time it takes to reach a particular interrupt request in the serial scan operation. Interrupt requests may be serially scanned one after another into the serial input. Thus, after the status of a particular interrupt request is serially scanned into the interrupt controller, there is a delay or latency while the other interrupt requests are being scanned before the status of that particular interrupt request is again updated during the next scan cycle. This latency provides a window where an end of interrupt (EOI) may be received by the interrupt controller prior to the clearing of the interrupt source that requested the interrupt associated with the EOI. The interrupt may have already been cleared in the device that initially asserted the interrupt request, but due to the scan latency the interrupt request may still appear asserted to the interrupt controller. Thus, upon receiving an EOI the interrupt controller may believe that a new interrupt is being requested and thus generate a spurious interrupt. To avoid this spurious interrupt, a mask may be enabled of duration relative to the scan latency to disable the serial scan input from indicating an active interrupt request after an EOI is received. The serial scan interrupt request input may be masked, or ignored, for an amount of time after an EOI to allow the status of the serially scanned interrupt request to be updated before any new interrupt requests are acknowledged by the interrupt controller. The amount of time for which interrupt requests are masked at the serial input may correspond to the maximum scan latency or may be programmable for a varying amount of time. If the interrupt source is still active at the end of the mask duration, then the interrupt controller may assume that a new interrupt is desired and thus treat the interrupt request as a new active interrupt request. In one embodiment, all serial scanned interrupt requests may be disabled for an amount of time upon receiving an EOI. In another embodiment, only interrupt requests corresponding to the interrupt associated with the EOI are masked. Also, if all interrupt requests are inactive upon receiving an EOI no masking is necessary.
In addition to an interrupt controller, a computer system may included a posted write buffer in a bus interface unit for posting write cycles to peripheral devices or to functional units, such as a DMA controller or timer within the bus interface device. A posted write buffer allows write cycles to complete more quickly on a source bus by quickly accepting the write into the posted write buffer and then later completing the write to the internal device or to the target bus. If a write that is posted is a write to a peripheral device or functional unit to clear an interrupt that has been or is being serviced and an EOI for that interrupt is received at the interrupt controller, then the delay of posting the write in the write buffer may cause the EOI to be received at the interrupt controller before the write to clear the interrupt request has reached it's destination. Thus, the interrupt request may still be asserted when the EOI is received by the interrupt controller even though a write to clear the interrupt was sent before the EOI. The interrupt controller may therefore assert a spurious interrupt since the interrupt reque
Ferguson Patrick L.
Heinrich David F.
Rawlins Paul B.
Woods Robert L.
Compaq Computer Corp.
Conley Rose & Tayon PC
Kowert Robert C.
Myers Paul R.
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