Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-07-09
2004-11-02
Nguyen, Van Thu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S046000, C365S148000, C365S189011, C365S236000
Reexamination Certificate
active
06813208
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuits, and more specifically to sensing data stored in an integrated circuit memory device.
BACKGROUND OF THE INVENTION
Computer systems, video games, electronic appliances, digital cameras, and myriad other electronic devices include memory for storing data related to the use and operation of the device. A variety of different memory types are utilized in these devices, such as read only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory (FLASH), and mass storage such as hard disks and CD-ROM or CD-RW drives. Each memory type has characteristics that better suit that type to particular applications. For example, DRAM is slower than SRAM but is nonetheless utilized as system memory in most computer systems because DRAM is inexpensive and provides high density storage, thus allowing large amounts of data to be stored relatively cheaply. A memory characteristic that often times determines whether a given type of memory is suitable for a given application is the volatile nature of the storage. Both DRAM and SRAM are volatile forms of data storage, which means the memories require power to retain the stored data. In contrast, mass storage devices such as hard disks and CD drives are nonvolatile storage devices, meaning the devices retain data even when power is removed.
Current mass storage devices are relatively inexpensive and high density, providing reliable long term data storage relatively cheap. Such mass storage devices are, however, physically large and contain numerous moving parts, which reduces the reliability of the devices. Moreover, existing mass storage devices are relatively slow, which slows the operation of the computer system or other electronic device containing the mass storage device. As a result, other technologies are being developed to provide long term nonvolatile data storage, and, ideally, such technologies would also be fast and cheap enough for use in system memory as well. The use of FLASH, which provides nonvolatile storage, is increasing popular in many electronic devices such as digital cameras. While FLASH provides nonvolatile storage, FLASH is too slow for use as system memory and the use of FLASH for mass storage is impractical, due in part to the duration for which the FLASH can reliably store data as well as limits on the number of times data can be written to and read from FLASH.
Due to the nature of existing memory technologies, new technologies are being developed to provide high density, high speed, long term nonvolatile data storage. One such technology that offers promise for both long term mass storage and system memory applications is Magneto-Resistive or Magnetic Random Access Memory (MRAM).
FIG. 1
is a functional diagram showing a portion of a conventional MRAM array
100
including a plurality of memory cells
102
arranged in rows and columns. Each memory cell
102
is illustrated functionally as a resistor since the memory cell has either a first or a second resistance depending on a magnetic dipole orientation of the cell, as will be explained in more detail below. Each memory cell
102
in a respective row is coupled to a corresponding word line WL, and each memory cell in a respective column is coupled to a corresponding bit line BL. In
FIG. 1
, the word lines are designated WL
1
-
3
and the bit lines designated BL
1
-
4
, and may hereafter be referred to using either these specific designations or generally as word lines WL and bit lines BL. Each of the memory cells
102
stores information magnetically in the form of an orientation of a magnetic dipole of a material forming the memory cell, with a first orientation of the magnetic dipole corresponding to a logic “1” and a second orientation of the magnetic dipole corresponding to a logic “0.” The orientation of the magnetic dipole of each memory cell
102
, in turn, determines a resistance of the cell. Accordingly, each memory cell
102
has a first resistance when the magnetic dipole has the first orientation and a second resistance when the magnetic dipole has the second orientation. By sensing the resistance of each memory cell
102
, the orientation of the magnetic dipole and thereby the logic state of the data stored in the memory cell
102
can be determined.
To write data to a selected memory cell
102
, a row current IROW is applied to the word line WL coupled to the cell and a column current ICOL is applied to the bit line BL coupled to the cell. The row current IROW and column current ICOL generated respective magnetic fields, with only the selected memory cell
102
being subjected to both the magnetic field generated by the row current and the magnetic field generated by the column current. The combination of these magnetic fields applied to the selected memory cell
102
sets the orientation of the magnetic dipole and thereby the resistance of the cell, which writes a data bit corresponding to either a logic 1 or 0 into the cell.
To read data from the MRAM array
100
, the resistance of a selected memory cell
102
must be sensed. In one method of sensing the resistance of a selected memory cell
102
, a reference voltage VA is applied to the word line WL coupled to the cell, and all other word lines and unselected bit lines BL are coupled to ground.
FIG. 1B
is a schematic illustrating the equivalent circuit of the MRAM array
100
when the memory cell
102
coupled to the word line WL
2
and bit line BL
3
is selected. In this situation, the reference voltage VA is applied to the selected word line WL
2
, and all other word lines WL
1
, WL
3
and unselected bit lines BL
1
, BL
2
, BL
4
are coupled to ground. The resistance of the selected memory cell
102
is represented by the resistance RSC, which is coupled between word line WL
2
and bit line BL
3
. All unselected memory cells
102
coupled to the selected bit line BL
3
are coupled between the bit line BL
3
and the unselected word lines WL
1
, WL
3
, which are coupled to ground, and these unselected memory cells collectively form a “sneak” resistance RSN. All other unselected memory cells
102
in the array
100
do not affect the equivalent circuit since both ends of these memory cells are coupled to ground via the unselected word lines WL
1
, WL
3
, and bit lines BL
1
, BL
2
, and BL
4
, as will be appreciated by those skilled in the art.
In response to the applied reference voltage VA, a read current IR flows through the resistance RSC presented by the selected memory cell
102
and through the sneak resistance RSN to ground. The current IR generates a sense voltage SV on the selected bit line BL
3
, with the magnitude of this voltage being a function of the magnitude of the resistance RSC of the selected memory cell
102
. When the resistance RSC has a larger value, the sense voltage SV on the bit line BL
3
will be less than when the resistance RSC has a smaller value. Accordingly, the sense voltage SV has a value indicating the magnitude of the resistance RSC and thus indicating the logic state of the data stored in the selected memory cell
102
.
In theory, sensing the resistance value of a selected memory cell
102
to read the logic state of data stored in the cell is simple as just described. In practice, however, reliable sensing is difficult due, in part, to the relatively small change in the resistance of the memory cell
102
between logic states. For example, in a typical MRAM array, each memory cell
102
has a resistance of about 1 Megaohm when the cell stores a logic “1” and a resistance of about 1.1 Megaohms when the cell stores a logic “0.” The differential resistance of the selected memory cell
102
between a logic “1” and a logic “0” is thus only about 100 K&OHgr; or approximately 10%. As a result, the sense voltage SV developed on the bit line BL
3
varies by this same amount, making it difficult to reliably detect the sense voltage and determine whether a selected memory cell
102
stores a logic 1 or 0, as will be appreciated by those skilled in the ar
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Van Thu
LandOfFree
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