Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-03-19
2001-11-20
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S165000, C711S170000, C703S015000, C703S021000, C703S022000
Reexamination Certificate
active
06321295
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to a device and method for selectively transferring or filtering data between storage mediums using the application data itself with dynamic memory allocation to make the selection or create the filter criteria.
BACKGROUND OF THE INVENTION
The electronics field is becoming more competitive. New entrants to the market are generating tremendous pressure to increase efficiency of logic design, to reduce design cost, and, to reduce time to market. Extensive performance of simulation can detect design errors before a design is manufactured, and thus reduce the number of design iterations. The use of an efficient hardware description language (HDL) such as VERILOG® and a host simulation system has become invaluable for minimizing design errors, and has made it possible to fabricate functional chips in the first silicon processed.
Computers, used as a host for a logic simulation program, in one example, employ a hierarchical information retrieval method for transferring information or data between storage devices. One of the storage devices is typically a mass storage device, such as a hard disk. Another of the storage devices usually comprises a relatively faster and more accessible storage device such as random-access memory (RAM). Finally, an intermediate storage device, such as a cache on a microprocessor, is used to provide rapid, but usually very small, data transfers between the hard disk and random-access memory. The random-access memory is normally smaller than a hard disk and is usually a faster and more accessible storage device The relative size between the cache and the random-access memory varies. On a personal computer, the cache is usually smaller than the random access memory. On workstations and microcomputers, the cache is usually larger than the random access memory. Such a pattern commonly exists notwithstanding a use of multiple levels of hierarchy.
Common retrieval methods employ paging, swapping, or caching to improve the utilization storage devices by reversibly transferring large blocks of information between the storage devices. While these retrieval methods normally improve the efficiency of a logic simulation program, that improved efficiency is merely a side effect rather than an intended purpose.
In prior logic simulation programs, the host simulation system uses a static memory allocation algorithm in the hardware description language, VERILOG, which requires the employment of a random-access memory (hereinafter referred to as a “memory array”) of a size at least equal to the entire simulated memory size. Thus, the permitted size of information or data transfers is determined largely by the physical size of the memory array. If, for example, a 128 megabit hard memory device is called for by the logic simulation program and the memory array has enough capacity, the entire contents of the hard memory device is transferred into the memarray. This can create substantial inefficiencies, especially with hard memory devices that are large.
Prior logic simulation programs are limited to either using expensive, large memory arrays or performing the time-consuming operation of transferring the contents of relatively small increments of memory to the memory array, regardless of the usefulness of a particular memory increment. A need exists for a logic simulation program that does not use a full memory transfer like that utilized by the static memory allocation algorithm. Accordingly, the present invention provides a dynamic memory allocation algorithm for the hardware description language, i.e., VERILOG, that adjusts the amount of data transferred to the memory array, and, for example, can transfer less than the entire contents of a hard memory device in a logic simulation program. Fewer data transfers are made to the memory array. Thus, the total size of the data transferred to the memory array, in a logic simulation program employing the present invention the present invention, is a much smaller than the entire size of the memory that is simulated.
SUMMARY OF THE INVENTION
Hardware description language (HDL) such as VERILOG, does not have a dynamic memory allocation scheme in its native format. This forces designers to use the static memory allocation scheme when they choose to use the standard HDL, i.e., VERILOG. Through employment of the present invention, a logic simulation program, in which circuit information is described with an HDL such as VERILOG, can use the circuit information both as input to a circuit simulation and as addressing information. The addressing information is then used to provide hierarchical information retrieval within the simulation data, thereby reducing the amount of data that is to be transferred between a storage device, such as a cache (hereinafter referred to as a “dump memory”), and a storage device, such as a memory array. Since the amount of data that needs to be transferred is reduced, the time required for transferring this data is consequently reduced, thereby increasing the efficiency of the logic simulation program utilizing the storage devices. The use of the addressing information also reduces the size required of a dump memory and a memory array for a certain performance.
The present invention also uses the circuit information for partitioning structures, such as in hard memory devices, into more convenient sizes for simulation, for instance, by a logic simulation program. The addressing information may also be used for generating tables of information about the structure of the objects, such as in hard memory, which are to be partitioned or paged into a memory array. This further enhances the speed of and reduces the size of information transfers.
The present invention in one aspect provides an article for selectively transferring application data between storage means in a computer system. The article includes first data storage means and second data storage means. The first data storage means stores the application data and non-application data. The second data storage means receives a dump of at least a part of the application and non-application data from the first data storage means. The article includes means for examining the data in the second data storage means to identify the application data and derive a secondary address for the application data. A third data storage means receives, and means of the article parses, only the application data from the second data storage means which are indicated by the secondary address. The article includes the means for parsing the application data and further includes means for transferring the parsed application data from the third data storage means to the second data storage means. The parsed application data and remaining non-application data are transferred from the second data storage means to the first data storage means. Any remaining unexamined data is dumped from the first data storage means to the second storage means.
A more specific application of the present invention is a simulation device for dynamically simulating hard memory in software of a computer system. The device includes a mass memory device that stores application data and non-application data and a dump memory that receives a dump of at least a part of the application data and the non-application data from the mass memory device. A memory controller examines data in the dump memory to identify the application data and derive a secondary address for the application data. A memory array receives only the application data from the dump memory indicated by the secondary address. The memory controller parses only the application data indicated by the secondary address. The parsed application data is transferred from the memory array to the dump memory. The parsed application data and the remaining non-application data is transferred from the dump memory to the mass memory device. Any remaining unexamined data is dumped from the mass memory device to the dump memory.
A method for selectively transferring application data between storage mean
Gossage Glenn
inSilicon Corporation
Rupert Douglas S.
Wildman Harrold Allen & Dixon
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