Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-12-02
1999-04-06
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711146, 395296, 395375, 36472502, G06F 1200
Patent
active
058931457
ABSTRACT:
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.
REFERENCES:
patent: 3701977 (1972-10-01), Mendelson et al.
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4725973 (1988-02-01), Matsuura et al.
patent: 4782441 (1988-11-01), Inagami et al.
patent: 4849882 (1989-07-01), Aoyama et al.
patent: 4884197 (1989-11-01), Sachs et al.
patent: 4891754 (1990-01-01), Boreland
patent: 5073864 (1991-12-01), Methvin et al.
patent: 5181183 (1993-01-01), Miyazaki
patent: 5187796 (1993-02-01), Wang et al.
patent: 5193167 (1993-03-01), Sites et al.
patent: 5226171 (1993-07-01), Hall et al.
patent: 5235536 (1993-08-01), Matsubishi et al.
patent: 5251323 (1993-10-01), Isobe
patent: 5335330 (1994-08-01), Inoue
patent: 5434592 (1995-07-01), Dinwiddie, Jr. et al.
patent: 5453945 (1995-09-01), Tucker
patent: 5471637 (1995-11-01), Pawlowski
patent: 5511219 (1996-04-01), Shimony et al.
patent: 5513366 (1996-04-01), Agarwal et al.
patent: 5537640 (1996-07-01), Pawlowski
patent: 5627981 (1997-05-01), Adler et al.
patent: 5640588 (1997-06-01), Vegesna et al.
patent: 5644520 (1997-07-01), Pan et al.
patent: 5655096 (1997-08-01), Branigin
patent: 5673408 (1997-09-01), Shebanow et al.
patent: 5673426 (1997-09-01), Shen et al.
patent: 5692211 (1997-11-01), Guilick et al.
Kdohn, L, et al., "The Visual Instruction Set (VIS) in UltraSPARC," SPARC Technology Business -Sun Microsystems, Inc., 1996 IEEE, pp. 462-489.
Gwennap Linley, "UltraSparc Adds Multimedia Instructions -Other New Instructions Handle Unaliqned and Little-Endian Data," Microprocessor Report, Dec. 5, 1994, pp. 16-18.
Lee, Ruby B., "Realtime MPEG Video via Software Decompression on a PA-RISC Processor," Hewlett-Packard Company, 1995 IEEE, pp. 186-192.
Mattison, Phillip E., "Practical Digital Video With Programming Examples in C," Wiley Professional Computing, pp. 158-178.
Zhou, Chang-Guo, et al., "MPEG Video Decoding With the UltraSPARC Visual Instruction Set," Sun Microsystems, Inc., 1995 IEEE, pp. 470-474.
Longhenry Brian E.
Thayer John S.
Thome Gary W.
Advanced Micro Devices , Inc.
Compaq Computer Corp.
Daffer Kevin L.
Namazi Mehdi
Swann Tod R.
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