Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-02-13
2007-02-13
Fadmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S003000, C711S119000, C711S134000, C711S140000, C711S142000, C711S143000, C711S144000, C711S145000, C711S151000, C711S150000
Reexamination Certificate
active
10760436
ABSTRACT:
Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests provided according to a second cache coherency protocol, the second cache coherency protocol being different from the first cache coherency protocol. The first node provides a response to a given one of the requests to the first node that varies based on the condition detected by the detector.
REFERENCES:
patent: 5802577 (1998-09-01), Bhat et al.
patent: 5829040 (1998-10-01), Son
patent: 5875467 (1999-02-01), Merchant
patent: 5875472 (1999-02-01), Bauman et al.
patent: 5958019 (1999-09-01), Hagersten et al.
patent: 6055605 (2000-04-01), Sharma et al.
patent: 6085263 (2000-07-01), Sharma et al.
patent: 6108737 (2000-08-01), Sharma et al.
patent: 6345342 (2002-02-01), Arimilli et al.
patent: 6457100 (2002-09-01), Ignatowski et al.
patent: 6490661 (2002-12-01), Keller et al.
patent: 6631401 (2003-10-01), Keller et al.
patent: 2001/0034815 (2001-10-01), Dungan et al.
patent: 2002/0009095 (2002-01-01), Van Doren et al.
patent: 2002/0073071 (2002-06-01), Pong et al.
patent: 2002/0129211 (2002-09-01), Arimilli et al.
patent: 2003/0018739 (2003-01-01), Cypher et al.
patent: 2003/0140200 (2003-07-01), Jamil et al.
patent: 2003/0145136 (2003-07-01), Tierney et al.
patent: 2003/0195939 (2003-10-01), Edirisooriya et al.
patent: 2003/0200397 (2003-10-01), McAlister et al.
patent: 2004/0002992 (2004-01-01), Cypher et al.
patent: 2005/0251631 (2005-11-01), Rowlands et al.
Rajeev, Joshi, et al., “Checking Cache-Coherence Protocols with TLA+ ”, Kluwer Academic Publishers, 2003, pp. 1-8.
Martin, Milo M.K., et al., “Token Coherence: Decoupling Performance and Correctness”, ISCA-30, pp. 1-12, Jun. 9-11, 2003.
Acacio, Manuel E., et al., “Owner Prediction for Accelerating Cache-to-Cache Transfer Misses in a cc-NUMA Architecture”, IEEE 2002.
Gharachorloo, Kourosh, et al., “Architecture and Design of AlphaServer GS320”, Western Research Laboratory, (Date Unknown).
Gharachlorloo, Kourosh, et al., “Memory Consistency and Event Ordering In Scalable Shared-Memory Multiprocessors”, Computer Systems Laboratory, pp. 1-14, (Date Unknown).
Steely, Jr. Simon C.
Tierney Gregory Edward
Van Doren Stephen R.
Chery Mardochee
Fadmanabhan Mano
Hewlett--Packard Development Company, L.P.
LandOfFree
System and method for responses between different cache... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for responses between different cache..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for responses between different cache... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3876921