Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-09-30
2002-08-27
Wong, Peter (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S313000, C710S307000, C710S033000, C710S034000
Reexamination Certificate
active
06442643
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, generally, to systems and methods for transferring data across different data buses, and in particular embodiments, to methods for transferring data formatted for a Peripheral Component Interconnect (PCI) data bus across a non-PCI data bus, and systems incorporating the same.
2. Description of Related Art
Modern processor-based systems often use standardized bus architectures for transferring data. For example, ASB is a bus standard developed by Advanced RISC Machines (ARM) for use with their ARM9 series of processors. ASB is typically used in low power applications such as system-on-a-chip applications. PCI is an industry standard input/output (I/O) bus specification typically used in higher-power applications such as connecting peripherals to a personal computer (PC) or workstation.
It is often useful to design processor-based systems that utilize both of these bus standards. For example, in the design of set-top boxes, an ARM processor may be used in conjunction with an ASB bus to transfer data from a peripheral to memory. However, greater connectivity may be achieved if one of the peripherals is a PCI interface. With a PCI as one of the peripherals, the set-top box can be connected to PCI-compatible peripherals such as a modem, an Ethernet controller, or some other digital data source.
FIG. 1
is a block diagram of an example set-top box system
10
utilizing both ASB and PCI buses. As illustrated in
FIG. 1
, within a primary integrated circuit (IC)
12
—in essence a system on a chip—is an ARM processor
14
coupled to an ASB. The ASB is comprised of a data bus BD
16
and an address bus BA
18
. Also within the IC
12
and coupled to the ASB is a PCI I/O interface
20
and a memory controller
22
. The PCI I/O interface
20
may be connected off-chip to other peripherals such as modems
24
, Ethernet controllers
26
, storage subsystems
28
, graphics cards
30
, or other external devices through a PCI address/data (A/D) bus
32
, which can function as both an address and data bus. The Ethernet controller
26
or modem
24
might be used for connecting to the Internet to provide the set-top box system
10
with web surfing capability.
In addition, video data may be transferred through the PCI I/O interface
20
to a video card
34
such that, rather than being a component of a set-top box system
10
, the IC
12
could reside on a plug-in card for executing Motion Picture Experts Group (MPEG) audio/video decompression, with the PCI I/O interface
20
sending video data to video cards
34
in a PC system to display the images on-screen.
The memory controller
22
is coupled to off-chip synchronous dynamic random access memory (SDRAM)
36
for storing information transferred over the ASB bus.
The IC
12
may have dedicated ports for connecting to a satellite front end
38
to receive high-speed video and audio data
42
. In such a configuration, a data parser
40
receives the audio and video data
42
from the satellite front end
38
, parses out all the data packets, decides which data packets are to be stored, and then sends those data packets to the memory controller
22
for storing in the SDRAM
36
. However, it is also possible for data received through the satellite front end
38
to enter the set-top box system
10
through the Ethernet controller
26
and PCI I/O interface
20
.
An audio/video block
44
within the IC
12
retrieves data from the SDRAM
36
, decompresses the data, outputs the audio data
46
, and communicates the video data to a display refresh module
48
. The display refresh module
48
then sends the video data
50
to an off-chip encoder
52
, which converts the digital video data into NTSC or PAL format for transmission to a video display device
54
.
An ASB system will now be described as an example of a non-PCI system. As noted above, the ASB is designed to operate in conjunction with the ARM processor
14
, which transfers 32 bits of data (one word) at a time. However, not all of the data bits in the word may be valid. The ARM processor
14
is capable of transferring one word of valid data, 16-bits (a half-word) of valid data, or 8-bits (one byte) of valid data in contiguous memory locations.
FIG. 2
is an illustration of the seven possible “byte patterns” that may be present when 32 bits of data (four bytes, denoted bytes
0
-
3
) appear on BD
16
, the shaded blocks representing valid bytes. One possible pattern is a word transfer
56
, where all four bytes are valid. Another possible pattern is a half-word transfer of bytes
0
-
1
(reference character
58
) or bytes
2
-
3
(reference character
60
). The other possible transfer patterns are byte transfers
62
, where the valid byte can be any one of the four bytes. Note that the ARM bus can only transfer data in the patterns illustrated in FIG.
2
—for example, a half-word transfer can have either bytes
0
-
1
or bytes
2
-
3
valid, but it cannot have bytes
1
and
2
or bytes
0
and
3
valid.
Devices mastering the ASB must generate certain signals to describe which bytes in the transfer are valid. As illustrated in
FIG. 2
, one is a two-bit control signal called BSIZE, whose encodings are as follows: binary 00 means a byte transfer, binary 01 means a half-word transfer and binary 10 means a word transfer. Another signal is the two least significant bits of the address bus, BA[
1
:
0
]. BA[
1
:
0
] identifies, given a particular BSIZE, which of the four bytes in the 32-bit word being transferred are valid. It should be noted that in ASB format the address and data buses BA
18
and BD
16
are not shared because it is more efficient to have separate address and data buses, and because ASB is typically used within a chip where minimizing the number of pins is relatively unimportant.
As illustrated in
FIG. 2
, a BSIZE of binary 10 and a BA[
1
:
0
] of XX (X indicating don't cares) signifies that all bytes in the word being transferred are valid. For a BSIZE of binary 01, BA[
1
:
0
] can be either 0, signifying that bytes
0
-
1
(one half-word) are valid, or 1, signifying that bytes
2
-
3
(the other half-word) are valid. For a BSIZE of binary 00, BA[
1
:
0
] can be 00, signifying that byte 0 is valid, 01, signifying that byte
1
is valid, 10, signifying that byte
2
is valid, or 11, signifying that byte
3
is valid. The memory controller
22
decodes BSIZE and BA[
1
:
0
] to determine which bytes on BD are valid and should be transferred to memory.
For purposes of illustration,
FIG. 3
is a timing diagram of a half-word write transfer in a conventional ASB system. Referring to
FIG. 3
, BWRITE is a control signal generated by the device mastering the bus that indicates whether the operation is a read or a write. In the example of
FIG. 3
, a high state indicates a write operation, while a low state indicates a read operation. BSIZE, as described above, is a two-bit control signal also generated by the device mastering the bus that indicates whether the valid data being transferred is a byte, half-word, or word transfer. BA, as described above, is the 32-bit address bus. BTRAN is a 2-bit control signal, driven only during the first half of a clock cycle, that determines what kind of a transfer is on the bus. In the example of
FIG. 3
, binary 00 indicates no transfer (the bus is idle), a binary 11 indicates a sequential transfer, and a binary 10 indicates a non-sequential transfer. It should be noted that the ARM processor
14
does not use non-sequential transfers, which simplifies the decoding of BTRAN. BWAIT is a control signal, driven by the slave device (the memory controller
22
in
FIG. 1
) in response to signals from the master only during the second half of a clock cycle, that indicates whether the slave device is ready to respond or not. In the example of
FIG. 3
, a high state indicates that the slave device is not ready, while a low state indicates that the slave device is ready. BD, as described above, is the
Conexant Systems Inc.
Foley & Lardner
Phan Raymond N
LandOfFree
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