Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-12-14
1998-10-13
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711141, 711145, G06F 13376
Patent
active
058227652
ABSTRACT:
A data processing system and method having a number of cache controllers coupled to a bus. A cache controller uses a buffer operably coupled to the bus for loading information from the bus. A status bit associated with a buffer indicates the buffer status. The cache controller has logic circuitry operably coupled to the bus and the buffer. The logic circuitry responds to a certain cache coherency operation by loading the buffer and waiting during a predetermined interval for a possible retry signal before further processing the operation.
REFERENCES:
patent: 5276852 (1994-01-01), Callander et al.
patent: 5404483 (1995-04-01), Stamm et al.
patent: 5442754 (1995-08-01), Datwyler et al.
patent: 5442763 (1995-08-01), Bartfai et al.
Boatright Bryan David
Feiste Kurt Alan
Merkel Lawrence Joseph
Williams Derek Edward
Chan Eddie P.
England Anthony V.S.
International Business Machines - Corporation
Wallace George F.
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