System and method for reliable system shutdown after coherency c

Details System and method for reliable system shutdown after coherency c System and method for reliable system shutdown after coherency c

1997-11-25

2000-06-06

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

714 5, G06F 1208

Patent

active

060732164

ABSTRACT:
There is disclosed a memory control circuit for use in a processing system containing a plurality of processors coupled to a main memory by a common bus. The memory control circuit is adapted for implementing directory-based coherency in the processing system according to a selected coherency algorithm and comprises: 1) monitoring circuitry for detecting coherency corruption in a coherency directory associated with the main memory; and 2) coherency control circuitry responsive to a detection of coherency corruption in the coherency directory for dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner. In some embodiments, the monitoring circuitry further detects possible system coherency failure conditions external to the coherency directory and the coherency control circuitry responds to the detection of a possible system coherency failure condition by dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner.

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patent: 5544345 (1996-08-01), Carpenter et al.
patent: 5581729 (1996-12-01), Nishtala et al.
patent: 5615353 (1997-03-01), Lautzenheiser

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