Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-04-04
2001-07-31
Nelms, David (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S207000, C365S208000, C365S149000, C365S222000
Reexamination Certificate
active
06269039
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory devices, and more particularly to dynamic adjustment of a refresh interval of a memory device to minimize the average refresh power of the memory device.
2. Description of the Related Art
Memory devices, such as, dynamic random access memories (DRAMs) include a wide variety of applications. The use of DRAM memory is extremely attractive to many such applications due to its high density and low power access. When used in applications, the power needed to refresh the DRAM becomes a significant part of the standby power of the system. It is well known that the frequency of refresh needed to guarantee stored data integrity is a function of temperature and operating voltage (to the extent that the stored charge is a function of operating voltage). Conventional art usage of DRAM memory ensures refresh rates corresponding to the anticipated worst case values of these conditions. This results in refresh rates much higher than needed for a majority of actual operating conditions.
Hardwired refresh controllers, as used in prior art computer systems, generally lack the flexibility to alter this conventional art approach. However, in many applications the refresh of DRAM may be controlled via more sophisticated refresh controller logic embodied either as special purpose hardware or as a task running on a control or signal processor invoked by a timer event. The approach using a program on an embedded processor is attractive since the approach permits high priority processing to use the memory by deferring refresh while ensuring that the overall refresh rate remains within specifications. Both of these approaches provide flexibility to dynamically adjust the refresh rate, but still do not provide refreshing based on need. Instead, additional unnecessary refreshes are employed which can be expensive in terms of power dissipation, especially in systems, such as mobile systems, which employ batteries.
Therefore, a need exists for a system and method for reducing refresh rates of memory devices. A further need exists for sensing what is a minimum necessary value under current environmental conditions and manufacturing variations to initiate a refresh operation of the memory device.
SUMMARY OF THE INVENTION
A volatile memory device, in accordance with the present invention, includes an array of memory cells with at least two dummy cells disposed within the memory array. A driver is included for writing a first state to one of the at least two dummy cells and for writing a second state to another one of the at least two dummy cells. A comparison circuit compares the first state and the second state to a threshold to determine if a refresh of the array of memory cells is needed.
In alternate embodiments, a sample signal may be provided for enabling an output from the at least two dummy cells to be compared by the comparison circuit at a dynamically adjusted time interval. The dynamically adjusted time interval may include a sampling rate based on a result of a compare of the at least two dummy cells until the result of the compare changes value. The sample rate is preferably equal to a refresh rate of the memory array. The comparison circuit may include a sample signal line for enabling the comparison circuit to compare outputs of the at least two dummy cells. The comparison circuit may include an alert generator to generate an alert signal indicating a refresh of the memory array is needed. The threshold may be set such that discrimination between the first state and the second state stored on the dummy cells may be determined. The volatile memory may be included in a set of memory arrays.
Another volatile memory device, in accordance with the present invention, includes an array of memory cells and at least two dummy cells disposed within the array of memory cells. A write driver is coupled to the at least two dummy cells for writing a first state to one of the at least two dummy cells and for writing a second state to the other one of the at least two dummy cells. A comparison circuit is included for comparing the first state and the second state to a threshold to determine if a refresh of the array of memory cells is needed. A timing control device is also included for enabling outputs from the at least two dummy circuits to the comparison circuit in accordance with a sampling rate.
In alternate embodiments, the sampling rate may be based on a time interval between a last sample and a current sample such that the result of a comparison between the at least two dummy samples of the current sample has a different value than that of the last sample. The sample rate is preferably greater than or equal to a refresh rate of the memory array. The timing control device preferably enables the comparison circuit to compare the outputs of the at least two dummy cells. The comparison circuit may include an alert generator to generate an alert signal indicating a refresh of the memory array is needed. The threshold may be set such that discrimination between the first state and the second state stored on the dummy cells may be determined. The volatile memory may be included in a plurality of memory arrays. The timing control device may include one at least one of a processor, a controller and a logic circuit.
A method for optimizing refresh rate in memory devices, in accordance with the present invention, includes the steps of providing an array of memory cells with at least two dummy memory cells disposed within the memory array and initializing the at least two dummy cells with a first state and a second state of stored charge. A refresh interval for the memory array and a sampling interval for sampling the dummy cells are set. Stored charge of the dummy cells are compared to the threshold, after a sampling interval, to determine if a refresh is needed. The refresh interval is modified in accordance with the step of comparing.
In other methods, the memory array includes a plurality of groups of memory cells and may further the steps of refreshing a group of memory cells and setting a group index to indicate a next group awaiting to be refreshed at the next refresh interval. The step of comparing stored charge of the dummy cells to the threshold, after a sampling interval, to determine if a refresh is needed may include the step of enabling output of the stored charge of the dummy cells to a comparator to determine whether charge has leaked into or out of the dummy cells. The step of modifying the refresh interval may include the step of decreasing the refresh interval by a first increment and the sample interval by a second increment if a refresh is needed. The step of modifying the refresh interval may include the step of increasing the refresh interval by a first increment and the sample interval by a second increment if a refresh is not needed. The method may include the step of refreshing the dummy cells. The step of providing an array of memory cells with at least two dummy memory cells disposed within the memory array may include the step of providing a plurality of arrays of memory cells each including at least two dummy memory cells disposed within the memory array and further comprising the step of selecting an array of the plurality of arrays on which to perform the method steps.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
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Glossner, III Clair John
Hokenek Erdem
Meltzer David
Moudgill Mayan
International Business Machines Corp.
Nelms David
Yoha Connie C.
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