System and method for refreshing a DRAM device

Details System and method for refreshing a DRAM device System and method for refreshing a DRAM device

2007-11-06

2007-11-06

Graham, Kretelia (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100

Reexamination Certificate

active

11223194

ABSTRACT:
The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh operations and a refresh address counter that is coupled to the refresh control circuitry and that generates a refresh address in response to receiving a refresh request. The refresh address corresponds to a word line of the DRAM array to be refreshed. Address control and switching circuitry may be coupled to the refresh control circuitry. The address control and switching circuitry selectively transmits read/write addresses and refresh addresses to the DRAM array, in order to perform refresh operations on the DRAM array without inhibiting read and write operations.

REFERENCES:
patent: 5193072 (1993-03-01), Frenkil et al.
patent: 5835401 (1998-11-01), Green et al.
patent: 6646944 (2003-11-01), Shimano et al.
patent: 2005/0052928 (2005-03-01), Koshikawa

Affiliated with

Also associated with

Rating

System and method for refreshing a DRAM device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for refreshing a DRAM device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for refreshing a DRAM device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3862294