Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-03-15
2003-04-29
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S189020, C365S189120
Reexamination Certificate
active
06556490
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to memory compilers for semiconductor memories with redundant memory cells and fuses for storing faulty memory cell data, wherein the semiconductor memories are preferably provided for embedded System-On-Chip (SOC) applications.
2. Description of Related Art
Silicon manufacturing advances today allow true single-chip systems to be fabricated on a single die (i.e., System-On-Chip or SOC integration). However, there exists a “design gap” between today's electronic design automation (EDA) tools and the advances in silicon processes which recognizes that the available silicon real-estate has grown much faster than has designers' productivity, leading to underutilized silicon. Unfortunately, the trends are not encouraging: the “deep submicron” problems of non-convergent timing, complicated timing and extraction requirements, and other complex electrical effects are making silicon implementation harder. This is especially acute when one considers that analog blocks, non-volatile memory, random access memories (RAMs), and other “non-logic” cells are being required. The gap in available silicon capacity versus design productivity means that without some fundamental change in methodology, it will take hundreds of staff years to develop leading-edge integrated circuits (ICs).
Design re-use has emerged as the key methodology solution for successfully addressing this time-to-market problem in semiconductor IC design. In this paradigm, instead of re-designing every part of every IC chip, engineers can re-use existing designs as much as possible and thus minimize the amount of new circuitry that must be created from scratch. It is commonly accepted in the semiconductor industry that one of the most prevalent and promising methods of design reuse is through what are known as Intellectual Property (“IP”) components—pre-implemented, re-usable modules of circuitry that can be quickly inserted and verified to create a single-chip system. Such re-usable IP components are typically provided as megacells, cores, macros, embedded memories through generators or memory compilers, et cetera.
It is well-known that memory is a key technology driver for SOC design. Although providing high quality embedded memory IP in SOC applications poses several challenges, the total density of embedded memory has been increasing rapidly. It should be readily appreciated by those of ordinary skill in the art that without the use of redundancy, the fabrication yields of SOC devices and other embedded memory systems will be very low.
Several techniques exist for providing redundancy in conventional stand-alone, single-chip memories. In fact, such redundancy techniques have been largely responsible for the ever-increasing densities of the single-chip memories. Incorporating conventional redundancy schemes in embedded memory IP applications, however, has numerous shortcomings and drawbacks. First, providing redundancy using the existing techniques is a cost-effective solution only when the memory density is greater than a certain minimum number of bits. It is generally accepted that if the support circuitry needed for redundancy occupies more than 5% of the memory area, the design is not area-efficient.
It should be readily apparent that such requirements pose a great difficulty in the area of embedded memory design. For example, the embedded memories are typically provided in various sizes (i.e., densities) and distributed throughout the system (i.e., different memory instances). The requirement of redundancy in smaller memory instances, accordingly, would result in an unacceptably large redundancy overhead (that is, high area-inefficiency).
Further, conventional redundancy techniques typically involve placing fuse elements within the memory array for effectuating row redundancy and column redundancy. In general, they are placed in row decoders, faulty address storage areas, column fuse banks, et cetera. It should be readily appreciated that such schemes give rise to inefficient layouts because routing over fuse areas is not allowed, thereby causing routing congestion and related “place and route” problems. Also, because of the routing bottlenecks around the fuse areas, creating multi-level power grids may not be feasible in SOC circuits.
In addition, because there are limits to how small a laser-activated fuse element needs to be, the size of fuse elements does not scale in correspondence with the size of memory core cells. Relatedly, the pitch of fuses normally does not match the pitch of memory cells. Accordingly, it would be very difficult to tile fuses and connect fuses to periphery layouts, especially in the context of memory compilers that need to be highly flexible in terms of supporting different memory configurations and types for embedded applications.
Based on the foregoing, it should be readily apparent that there has arisen an acute need for a semiconductor memory architecture solution that advantageously overcomes these and other deficiencies of the prior art technologies as set forth hereinabove.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a scalable memory compiler for designing an arbitrary number and size of embedded memory instances with redundancy. It is a further object of the present invention to minimize area overhead associated with adding redundancy. Yet further object of the present invention relates to minimizing speed/performance impact due to redundancy. Still further objects of the present invention include: minimizing power consumption increase and maintaining zero power consumption, and providing flexibility in terms of fixing various types of defects.
In one aspect, the present invention is directed to a memory architecture having redundancy. A fuse box register (provided outside the memory macro) and an arbitrary number of memory instances are connected in a daisy chain. The fuse box register contains a plurality of fuses used for storing locations of defective rows and columns of a main memory array. During power-up or after blowing the fuses, the contents of the fuses (i.e., fuse data) are transferred to a plurality of volatile redundancy scan flip-flops. The fuse box register is then deactivated to eliminate quiescent current through the fuses. The redundancy scan flip-flops, connected in a scan chain, are located inside the fuse box register as well as the memory instances. During the shifting mode of operation, the fuse contents are scanned into individual flip-flops (organized as volatile scan registers) of the memory instances. Redundant elements are pre-tested by bypassing the fuses and directly scanning in arbitrary patterns into the redundancy scan flip-flops (override mode). Row and column redundancy is effectuated using the contents of the redundancy scan flip-flops.
In another aspect, the present invention is directed to a method of effectuating a redundancy scheme in a memory circuit. The redundancy method provides a fuse area outside a main memory area of the memory circuit, wherein the fuse area is used for storing fuse information corresponding to faulty locations of the main memory area. The method also provides a plurality of redundancy scan flip-flops in the main memory area. A redundant memory area of the memory circuit is pre-tested to verify its functionality. The main memory area is tested thereafter to determine faulty locations. Information corresponding the faulty locations is then stored in the fuse area. Upon power-up of the memory circuit, the redundancy scan flip-flops are reset and the fuse information is scanned into the flip-flops. Based on the fuse information stored in the plurality of redundancy scan flip-flops, the faulty locations in the main memory area are replaced with redundant locations.
In a further aspect, the present invention relates to an integrated semiconductor device which comprises a plurality of memory instances embedded in the
Hong Chang Hee
Shubat Alex
Danamraj & Youst P.C.
Elms Richard
Nguyen Tuan T.
Virage Logic Corp.
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