Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-27
2006-06-27
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07069528
ABSTRACT:
A method involves: detecting a timing violation in a timing path included in an integrated circuit design; removing a wire, which couples two nodes in the integrated circuit design and is included in the timing path; and routing a new wire between the two nodes. The new wire is longer than the removed wire. The method can also involve: calculating timing information (e.g., delay and/or slew information) for the wires included in the timing path and selecting the wire for removal dependent on the timing information. In some embodiments, such a method eliminates timing violations that arise due to crosstalk in a single post-timing-analysis routing pass.
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Buckles Jeffrey A.
Kovacs Attila
Campbell Stephenson Ascolese LLP
Dinh Paul
NEC Electronics America, Inc.
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