Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-10
2007-07-10
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
10721673
ABSTRACT:
A method of transforming a first topology to a reduced topology is disclosed. One preferred embodiment of the present invention includes a method of transforming a circuit from a first topology to a reduced topology, said first topology comprising a plurality of inter-connected circuit elements. The method comprises the steps of: (a) identifying one or more circuit elements; (b) analyzing the effect of reducing one or more of said identified circuit elements on the topological and physical characteristics of said circuit; and (c) if the effect satisfies a first standard, generating a second topology reflecting the reduction of one or more identified circuit elements.
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Kong Jun
McGaughy Bruce W.
Qin Wangguo
Yu Qingjian
Cadence Design Systems Inc.
Kik Phallaka
Morrison & Foerster / LLP
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