System and method for reducing short circuit current in a...

Details System and method for reducing short circuit current in a... System and method for reducing short circuit current in a...

2006-09-19

2006-09-19

Nguyen, Long (Department: 2816)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S108000, C326S131000

Reexamination Certificate

active

07109758

ABSTRACT:
A system for reducing a transition short circuit current in an inverter circuit includes a first inverter and a variable resistor set. The first inverter includes a first output node, a first PMOS device, and a first NMOS device. The variable resistor set biases the first inverter such that the first PMOS device is switched at a first time and the first NMOS device is switched at a second time, thereby substantially reducing the transition short circuit current. A method for reducing the transition short circuit current and a buffer circuit also are described.

REFERENCES:
patent: 4818901 (1989-04-01), Young et al.
patent: 5748019 (1998-05-01), Wong et al.
patent: 5760620 (1998-06-01), Doluca
patent: 6326819 (2001-12-01), Carlson
patent: 6437611 (2002-08-01), Hsiao et al.

Affiliated with

Also associated with

Rating

System and method for reducing short circuit current in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for reducing short circuit current in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for reducing short circuit current in a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3612267