Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-07-18
2006-07-18
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S128000, C711S003000, C711S155000, C711S119000, C711S113000, C711S118000, C709S216000, C710S200000
Reexamination Certificate
active
07080213
ABSTRACT:
A system and method for reducing shared memory write overhead in multiprocessor system. In one embodiment, a multiprocessing system implements a method comprising storing an indication of obtained store permission corresponding to a particular address in a store buffer. The indication may be, for example, the address of a cache line for which a write permission has been obtained. Obtaining the write permission may include locking and modifying an MTAG or other coherence state entry. The method further comprises determining whether the indication of obtained store permission corresponds to an address of a write operation to be performed. In response to the indication corresponding to the address of the write operation to be performed, the write operation is performed without invoking corresponding global coherence operations.
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Grenholm Oskar
Hagersten Erik E.
Radovic Zoran
Chery Mardochee
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Padmanabhan Mano
Sun Microsystems Inc.
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