System and method for reducing power consumption of memory...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration

Reexamination Certificate

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C710S002000, C710S005000, C710S015000

Reexamination Certificate

active

07991921

ABSTRACT:
A memory system for an I/O controller which includes a memory with multiple memory blocks, a supply voltage control circuit providing power to each memory block, and control logic. Each memory block retains stored information with reduced power consumption when receiving a reduced voltage level. The control logic allocates buffers in the memory and controls the supply voltage control circuit to provide the full voltage level to at least one memory block of at least one allocated buffer and to provide the reduced voltage level to remaining memory blocks. Each memory block includes one or more buffers. In various embodiments the control logic fully powers each memory block of a buffer or less than all of the memory blocks. A linked buffer structure may be used to reduce the memory blocks of an allocated buffer receiving full power, such as only one memory block in the buffer.

REFERENCES:
patent: 6647502 (2003-11-01), Ohmori
patent: 7134028 (2006-11-01), Bose et al.
patent: 7663961 (2010-02-01), Rowlands et al.
patent: 2002/0133677 (2002-09-01), Choi
patent: 2003/0206553 (2003-11-01), Surcouf et al.
patent: 2004/0143769 (2004-07-01), Deng et al.
patent: 2009/0027989 (2009-01-01), Michalak et al.
Le Cai, Energy Management Using Buffer Memory for Streaming Data, Feb. 2005, ieeexplore.org, vol. 24 [online, accessed on Mar. 25, 2011] URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=1386373&userType=inst.
Flautner, Krisztian et al. “Drowsy Caches: Simple Techniques for Reducing Leakage Power.” Proceedings of the 29thannual International Symposium on Computer Architecture. IEEE 2002 pp. 148-157.

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