System and method for reducing power consumption in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S758000, C714S759000, C714S799000, C375S287000

Reexamination Certificate

active

07613981

ABSTRACT:
A system and method for reducing power consumption in a Low Density Parity-Check Code (LDPC) decoder includes a sleep mode checking module and a gating circuit. The sleep mode checking module checks whether a check node is in sleep mode. The check node is considered to be in sleep mode when the absolute value of the message going to each of the one or more bit nodes corresponding to the check node is greater than a threshold value. The gating circuit turns OFF a Check Node and Bit Node Update Unit (CNBNU) associated with the check node when the check node is in the sleep mode. Turning OFF a CNBNU stops the exchange of messages between the check node and its corresponding one or more bit nodes.

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R.Bresnan et al., Efficient LDPC Decoding, Irish signals and systems conference 2004, Belfast. Jun. 30-Jul. 2. 6 pages.

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