Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2011-08-09
2011-08-09
Nguyen, Dang T (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S203000, C365S228000
Reexamination Certificate
active
07995415
ABSTRACT:
A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.
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Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Dang T
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