System and method for reducing power consumption associated...

Details System and method for reducing power consumption associated... System and method for reducing power consumption associated...

2007-05-15

2007-05-15

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S037000, C326S041000

Reexamination Certificate

active

11033612

ABSTRACT:
Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding plurality of input selection circuits. A plurality of additional inputs corresponding to the plurality of input selection circuits may also be received. In one embodiment, each input selection circuit is configured to output a corresponding input signal if a corresponding control signal is asserted and a timing signal is made available to the input selection circuit. To avoid unnecessary power consumption associated with the capacitance of various portions of the multiplexer, the timing signal is only asserted to a portion of the multiplexer at any given clock cycle according to the values of the control signals.

REFERENCES:
patent: RE36839 (2000-08-01), Simmons et al.
patent: 7075332 (2006-07-01), Young et al.
patent: 06-140853 (1994-05-01), None
patent: 10-340127 (1998-12-01), None
patent: 2000-293504 (2000-10-01), None
patent: 2003-67078 (2003-03-01), None

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