System and method for reducing phase error in clocks produced by

Details System and method for reducing phase error in clocks produced by System and method for reducing phase error in clocks produced by

1999-03-18

2000-10-10

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

327158, 375376, G06F 104, H03L 706

Patent

active

061311685

ABSTRACT:
A circuit and method for reducing error in a delay locked loop (DLL) in which a plurality of outputs, each establishing a boundary between two consecutive phases, is accomplished by averaging an error present in one of the outputs over at least two phases established by the outputs. A pair of inverters are used to drive fight during a definable time period, which enables the circuitry to average the error over at least two phases, thus distributing the error that was present in one phase over at least two phases.

REFERENCES:
patent: 5832021 (1998-11-01), Kondo
patent: 5999576 (1999-12-01), Lee
patent: 6011822 (2000-01-01), Dreyer
patent: 6037812 (2000-03-01), Gaudet
patent: 6055287 (2000-04-01), McEwan

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