Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-07-20
2004-01-13
Padmanabhan, Mano (Department: 2183)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S120000, C711S145000
Reexamination Certificate
active
06678798
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to multi-processor computer systems and more particularly to a system and method for reducing memory latency during read requests.
BACKGROUND OF THE INVENTION
With a distributed shared memory system, it is important to reduce overall memory latency for read requests. A snoopy processor bus can introduce delay into the read latency as the read request may be satisfied locally by a processor on the local bus. Waiting for the local check on the availability of data associated with the read request increases memory latency in the case where the data is not available locally. Therefore, it is desirable to reduce this memory latency that occurs for read requests.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated by those skilled in the art that a need has arisen for a technique to reduce latency in a distributed shared memory computer system. In accordance with the present invention, a system and method for reducing memory latency during read requests are provided that substantially eliminate or greatly reduce disadvantages and problems associated with conventional read processing in a computer system.
According to an embodiment of the present invention, there is provided a method for reducing memory latency during read requests that includes issuing a read request for data from a first one of a plurality of processors on a local bus. The read request is forwarded to a memory directory associated with a home memory for the data. A determination is made as to whether the data is located at another one of the plurality of processors on the local bus and whether the data has been modified. If so, the data is provided to the first one of the plurality of processors from an identified co-located processor. The read request is processed but a read response generated therefrom is ignored and not sent to the first one of the plurality of processors.
The present invention provides various technical advantages over conventional read processing techniques. For example, one technical advantage is to determine whether data is available locally in response to a read request while still sending the read request out for processing. Another technical advantage is to reduce latency in the system while processing read requests. Other technical advantages may be apparent to those skilled in the art from the following figures, description, and claims.
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Culler et al. “Parallel Computer Architecture”, 1999 Morgan Kaufmann Publishers, pg. 553-589.
Huffman William A.
Kuskin Jeffrey S.
Baker Paul
Padmanabhan Mano
Silicon Graphics Inc.
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