System and method for reducing latency in a memory array...

Details System and method for reducing latency in a memory array... System and method for reducing latency in a memory array...

2006-03-17

2008-12-09

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189110, C365S189011

Reexamination Certificate

active

07463545

ABSTRACT:
A system and method are disclosed for reducing latency in asserting a word-line for read/write operations of a memory row in a memory array. One embodiment of the present invention includes a memory array decoder circuit. The memory away decoder includes a level-shifting NAND-gate operative to receive a plurality of pre-decode inputs having a first voltage range. The level-shifting NAND-gate is further operative to generate a level-shifted NAND output signal that is a NAND output of the plurality of pre-decode inputs and has a second voltage range that is greater than the first voltage range. The memory array decoder circuit also includes an output inverter operative to invert the level-shifted NAND output signal to generate a decode signal.

REFERENCES:
patent: 6490222 (2002-12-01), Choi et al.
patent: 7245550 (2007-07-01), Morzano et al.

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