Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-09-27
2005-09-27
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S168000, C711S169000
Reexamination Certificate
active
06950909
ABSTRACT:
A cache access mechanism/system for reducing contention in a multi-sectored cache via serialization of overlapping write accesses to different blocks of a cache line to enable accurate cache directory updates. When a first queue issues a write access request for a first block of a cache line, the first queue concurrently asserts a last_in_line signal identifying the first queue as the last sequential queue to request access to that cache line. If there is an active write access requests for the cache line, the first queue undertakes a series of operations to enable sequentially correct updates to the cache directory with all previous updates taken into consideration. Included in these operations are tracking the completion of the write access and the corresponding write to the associated cache directory and copying the cache directory state to be updated from the parent queue (rather than from the cache directory) so that the parent queue's update of the directory state is included (and not overwritten) when the first queue writes to the directory. The correct cache directory state is then stored within the associated cache directory.
REFERENCES:
patent: 6118608 (2000-09-01), Kakihara et al.
patent: 6434668 (2002-08-01), Arimilli et al.
patent: 6442653 (2002-08-01), Arimilli et al.
patent: 6687795 (2004-02-01), Arimilli et al.
Guthrie Guy Lynn
Williams Derek Edward
Padmanabhan Mano
Salys Casimer K.
Song Jasmine
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