Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2007-10-16
2007-10-16
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C713S400000, C713S401000, C713S500000, C713S501000, C377S106000, C327S141000, C327S144000, C327S152000, C327S297000, C327S298000
Reexamination Certificate
active
10750607
ABSTRACT:
In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal and the received non-divided input clock signal, the first output signal being associated with a first delay. The method further includes, at a delay line, receiving the non-divided input signal, delaying the non-divided input signal for a time substantially equivalent to the first delay, and generating a second output clock signal associated with a second delay substantially equal to the first delay. The method further includes: (1) receiving at a multiplexer the first output signal, the second output signal, and a select control signal indicating which of the first output signal or the second output signal to select; (2) selecting at the multiplexer either the received first output signal or the second output signal based on the select control signal; and (3) generating the selected first output signal or second output signal as a substantially balanced third output signal.
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Chau Minh G.
Song James S.
Thippana Achuta R.
Brady W. James
Shaw Steven A.
Sugent James F.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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