System and method for reducing access latency to shared...

Details System and method for reducing access latency to shared... System and method for reducing access latency to shared...

2006-04-11

2006-04-11

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S151000, C712S207000

Reexamination Certificate

active

07028142

ABSTRACT:
System and method for reducing access latency to a shared program memory. The program memory is shared by more than one processor. The system includes fetch buffers (one per processor), prefetch buffers (one per processor), program fetch logic units (one per processor), and an arbiter. Each fetch buffer stores local instructions that are local to an instruction being used by an associated processor. Each prefetch buffer stores subsequent instructions that are subsequent to the local instructions stored in an associated fetch buffer. Each program fetch logic unit determines from where to fetch a next instruction required by the associated processor. The arbiter arbitrates between instruction fetch requests received for the fetch buffers and the prefetch buffers from the various processors. The arbiter determines which of the instruction fetch requests will next gain access to the program memory. Such a system improves latency by assigning a higher priority to fetch requests over prefetch requests or data requests.

REFERENCES:
patent: 4755933 (1988-07-01), Teshima et al.
patent: 5375223 (1994-12-01), Meyers et al.
patent: 5473764 (1995-12-01), Chi
patent: 5630075 (1997-05-01), Joshi et al.
patent: 5682521 (1997-10-01), Kubosawa
patent: 5740368 (1998-04-01), Villalpando
patent: 5829042 (1998-10-01), Leung
patent: 5835967 (1998-11-01), McMahan
patent: 5948094 (1999-09-01), Solomon et al.
patent: 6138213 (2000-10-01), McMinn
patent: 6247107 (2001-06-01), Christie
patent: 6317811 (2001-11-01), Deshpande et al.
patent: 6367006 (2002-04-01), Tran

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