System and method for recovering a microprocessor from a locked

Details System and method for recovering a microprocessor from a locked System and method for recovering a microprocessor from a locked

1997-10-23

1999-10-05

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710108, 713502, G06F 1336, G06F 946

Patent

active

059616229

ABSTRACT:
A data processing system (10) and method is used to recover a CPU from faulty operation. A single timer (38) is used to enable recovery operations. When the timer (38) experiences a first time-out event, a software watchdog interrupt (28) is generated. If the software interrupt (28) is properly handled before another consecutive/subsequent watchdog time out occurs, normal software execution will resume. However, if the software watchdog interrupt is not processed and the watchdog timer (38) experiences a second time-out event while the watchdog time-out interrupt (28) is pending, the timer (38) will generate a bus transfer termination signal (30) and set a status bit (270) within a watchdog status register (44). This assertion of termination signal (30) and the setting of the bit (270) allows the microprocessor to determine that a locked bus state exists. In response to the signal (30) and the bit (270), the locked bus (one or more of busses 22, 24, and/or 26) will attempt to recover from the locked bus state.

REFERENCES:
patent: 4247894 (1981-01-01), Beismann et al.
patent: 4837702 (1989-06-01), Obrea
patent: 5579523 (1996-11-01), Tanaka

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