Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2006-04-17
2008-08-05
Ghebretinsae, Temesghen (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S376000, C327S148000
Reexamination Certificate
active
07409027
ABSTRACT:
An improved clock recovery system, phase-locked loop, and phase detector are provided as well as a method for generating charge pump signals. The clock recovery system includes a phase-locked loop. The phase-locked loop includes a phase detector and a voltage-controlled oscillator. The phase detector generates pump signals that change linearly with respect to differences between phases of an incoming signal and a clocking signal. The oscillator is coupled to receive the pump signals and produce a clocking signal at a frequency not exceeding the frequency of the incoming signal. For example, the oscillator can produce clocking signals at one-half the frequency of the incoming signal, where the incoming signal is preferably a maximum bit rate of a data signal from which the clock signal is recovered. The phase detector can include a first flip-flop and second flip-flop. The first flip-flop receives the incoming signal and a differential first pair of clocking signals, whereas the second flip-flop is coupled to receive a delayed incoming signal and a differential second pair of clocking signals. The differential second pair of clocking signals are delayed 90° from the first pair of clocking signals to present a phase detector that samples using a quadrature clocking signal generated from the oscillator.
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Cypress Semiconductor Corp.
Daffer Kevin L.
Daffer McDaniel LLP
Ghebretinsae Temesghen
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