Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reexamination Certificate
1999-05-14
2002-07-23
Heckler, Thomas M. (Department: 2185)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C710S008000, C713S600000
Reexamination Certificate
active
06425077
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to reading data from programmable logic devices, and more particularly to selecting a subset of data from a large block of data read from a PLD.
BACKGROUND
Field programmable gate arrays (FPGAs), first introduced by XILINX in 1985, are becoming increasingly popular devices for use in electronics systems. For example, communications systems frequently employ FPGAs for their re-programmability. In general, the use of FPGAs continues to grow at a rapid rate because FPGAs permit relatively short design cycles, reduce costs through logic consolidation, and offer flexibility through re-programmability. The capabilities of and specifications for XILINX FPGAs are set forth in “The Programmable Logic Data Book,” published in 1998 by XILINX, Inc., the contents of which is incorporated herein by reference.
Where once a typical FPGA design comprised perhaps 5,000 gates, FPGA designs with 50,000 gates are now common, and FPGAs supporting 300,000 to 1,000,000 gates are available. New challenges for testing and debugging designs implemented on the devices have accompanied the growth in PLDs, particularly FPGAs. For example, large configuration bitstreams must be manipulated to test the PLDs. Thus, additional off-PLD storage and increased programming time are undesirable side effects of the growing size of configuration bitstreams.
In a test sequence that is presently used for designs implemented on PLDs, the configuration bitstream is downloaded to the device, selected input signals are provided to the device while advancing the device clock at selected times, and the state of the device is read back after having advanced the clock and provided the input signals. The state data can then be compared to expected state data to verify proper operation of the design.
In some PLDs, the data read back from the PLD correspond by position to the configuration bitstream downloaded to the PLD. In other PLDs, the configuration bitstream includes commands to replicate portions of the bitstream, so the data read back from the PLD includes more bits than the original bitstream. In either case, bits in the configuration bitstream that were used to program resources such as lookup tables, multiplexers, and signal line connections, and to initialize storage elements such as flip-flops, correspond to data read back from the PLD. The bitstream read back from a PLD includes two kinds of data: (1) the configuration data for determining the configuration of the PLD, which can be verified immediately after the configuration has been loaded into the PLD, and (2) state information stored in the storage elements in the PLD. The states of storage elements will probably change while running the test even though the states of bits used to program the programmable resources will probably remain the same. Thus it may be desirable to repeatedly monitor states of some of the storage elements but not to monitor the configuration data.
Communication between a host computer and a PLD typically occurs through an interface cable that includes electronic devices. For example, the XChecker™ cable available from Xilinx, Inc. includes an FPGA situated in the interface cable. This XChecker interface cable can perform several functions: transfer data from a host computer to the destination PLD for configuring the PLD, verify that data has been properly transferred, and read back selected data from the PLD, store it, and transfer it to the host computer (a function useful for debugging).
To select the desired data from the data read back from the device, past practice included creating a mask file indicating which bits of the data comprise the desired data. Thus, in the XChecker interface cable is a memory sufficient for holding the mask file. The size of the mask file is at least as large as the size of the configuration bitstream. Thus, prior systems had to process and provide storage for a large mask file, which can be larger than 1 MB. As PLD devices become larger, the size of this memory must be increased. Further, the time required to load the mask file from a host computer into the memory of the interface cable is greater for larger devices.
The continued growth in number of programmable resources and storage elements in PLDs will require more storage for the data being read back from the PLD, and merely providing increased storage for the larger data file increases system costs. Furthermore, if the data file must be transferred via a serial bitstream to an interface device, the process could be very time consuming. Thus, a method that reduces both required memory and time for transferring data, as well as other related problems, is desirable.
The continued growth in number of programmable resources and storage elements in PLDs will require more storage for the mask file, and merely providing increased storage for the larger mask file increases system costs. Furthermore, if the mask file must be transferred via a serial interface (to an interface device, for example), the process could be very time consuming. Thus, a method that address the aforementioned problems, as well as other related problems, is desirable.
SUMMARY OF THE INVENTION
The invention provides a system and method for reading back data from a large programmable logic device (PLD). With the system and method of the invention, the size of memory required to store selected bits can be smaller, indeed much smaller, than the number of bits stored in the PLD. Further, the speed of communicating the smaller amount of selected information from the PLD to the host computer is typically much faster than in the prior art because an interface device is provided having a high communication rate to the PLD, so that only a small amount of information is communicated at the slower rate between the interface device and the host computer.
In one embodiment, a clock offset table having one or more clock offset values is constructed. Each clock offset value indicates a relative readback clock cycle at which a selected bit is read from the PLD. The data is read from the PLD at a rate of one bit per readback clock cycle, and the readback clock cycles are counted as the bits are read from the device. When the count of readback clock cycles equals an offset value, the bit is saved by the interface device. Other bits are not saved by the interface device.
In another embodiment, data is read from the PLD at a rate of eight bits per readback clock cycle. In this embodiment, offset values are specified in units of bytes rather than bits. At each readback clock cycle, data can of course be read back in words having any length expected by the host, and the offsets are specified in units of words.
In another embodiment, data to be read from the PLD are specified by specifying a combination of offset values and ranges of adjacent bits. All data bits are read from the PLD, unwanted bits are discarded, and the data bits corresponding to the respective offset values are selected.
A system for reading data from a PLD comprises a host data processing system, a memory, an FPGA, and a microcontroller. The host is arranged to generate a configuration bitstream and a clock offset table, the clock offset table having one or more clock offset values representing respective readback clock cycle offsets corresponding to bits to be selected from data read from the PLD. The microcontroller and FPGA are coupled to the host, the memory, and the PLD. The microcontroller is programmed to download the configuration bitstream from the host to the PLD, and store the clock offset table in the memory. The FPGA in response to a command from the microprocessor toggles the PLD to send bits of data at a rate of one bit, byte, or word per readback clock cycle, and selects bits bytes, or words based on the clock offset values. The host then retrieves the selected bits bytes, or words.
The above summary of the present invention is not intended to describe each disclosed embodiment of the present invention. The figures and detailed description that follow provide
Allamsetty Chakravarthy K.
Carmichael Carl H.
Le Thach-Kinh
Mandhania Arun K.
St. Pierre, Jr. Donald H.
Heckler Thomas M.
Maunu LeRoy D.
Xilinx , Inc.
Young Edel M.
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