System and method for re-starting a peripheral bus clock signal

Details System and method for re-starting a peripheral bus clock signal System and method for re-starting a peripheral bus clock signal

1993-09-22

2000-12-19

Myers, Paul R.

Electrical computers and digital processing systems: support

Computer power control

Power conservation

G06F 1300

Patent

active

06163848&

ABSTRACT:
A system and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus are provided that accommodate a power conservation technique in which a peripheral bus clock signal may be stopped. If an alternate bus master requires mastership of the peripheral bus when the peripheral bus clock signal is stopped, the alternate bus master asserts a clock request signal for re-starting the peripheral bus clock. The clock request signal is broadcasted on the peripheral bus and is accordingly received by a clock control circuit. The clock control circuit responsively causes the re-starting of the peripheral bus clock signal. Subsequently, the alternate bus master can generate a bus request signal that is synchronous to the peripheral bus clock signal to thereby obtain a grant signal from a bus arbiter unit. As a result, the peripheral bus clock signal can be stopped for power management while still accommodating alternate bus masters that must assert a synchronous bus request signal to obtain mastership of the peripheral bus.

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