System and method for re-ordering memory references for...

Details System and method for re-ordering memory references for... System and method for re-ordering memory references for...

2007-05-08

2007-05-08

Lane, Jack A. (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S105000, C711S158000, C365S230010

Reexamination Certificate

active

11434392

ABSTRACT:
A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

REFERENCES:
patent: 6157987 (2000-12-01), Krishnamurthy et al.
patent: 6288730 (2001-09-01), Duluk et al.
patent: 6289470 (2001-09-01), Tanaka
patent: 6298424 (2001-10-01), Lewchuk et al.
patent: 5863283 (1983-04-01), None

Affiliated with

Also associated with

Rating

System and method for re-ordering memory references for... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for re-ordering memory references for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for re-ordering memory references for... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3802917