Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
2006-05-16
2006-05-16
Lane, Jack A. (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S158000, C711S105000, C365S230010
Reexamination Certificate
active
07047391
ABSTRACT:
A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).
REFERENCES:
patent: 6157987 (2000-12-01), Krishnamurthy et al.
patent: 6288730 (2001-09-01), Duluk, Jr. et al.
patent: 6298424 (2001-10-01), Lewchuk et al.
Dally William J.
Rixner Scott W.
Crawford & Maunu PLLC
Crawford. Robert J.
Lane Jack A.
The Board of Trustees of the Leland Stanford Junior University
The Massachusetts Institute of Technology
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