Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2005-03-08
2005-03-08
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S233100, C365S236000
Reexamination Certificate
active
06865132
ABSTRACT:
A system and method are disclosed to add logic to the self-refresh control logic presently employed in DRAM devices to ensure that, upon transitions between self-refresh mode and operational mode, at least one row of memory cells due to be refreshed is refreshed during the wait state following issuance of the transition command. Conducting this refresh during this existing wait state eliminates both the concern as to whether rows have been refreshed within the mandated refresh interval and the time required to execute an auto-refresh of at least one row upon completion of the transition.
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JEDEC Standard No. 21-C, “SDRAM&SGRAM Architectural and Operational Features,” pp. 3.11.5-1 to 3.11.5.4-5, no date given.
Farrell Todd D.
Schaefer Scott
Dorsey & Whitney LLP
Lam David
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