System and method for qualifying a logic cell library

Details System and method for qualifying a logic cell library System and method for qualifying a logic cell library

2006-12-27

2009-06-16

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07549133

ABSTRACT:
A system and a method for qualifying a logic cell library storing process parameters and properties of a specific semiconductor FAB when the logic cell library is newly developed or modified is provided. The system for qualifying a logic cell library which qualifies a new library and a modified library, includes a format transformer for transforming formats of the new library and the modified library into formats suitable for a predetermined qualifier, a sample generator for creating a qualification cell sample capable of qualifying all cells by using cells of the new or modified library having a transformed format, a cell matching tool for performing a one-to-one cell comparison between cells of the new library and cells of an existing library, a function qualifier for determining whether or not a right value is output with respect to an input value in order to qualify a cell function of the new or modified library, a processing rate qualifier for measuring a time required from signal input to signal output in order to qualify a cell processing rate of the new or modified library, a power consumption qualifier for measuring power consumed during a process of a cell of the new or modified library, and an inter-qualifier for determining whether or not logical design information and physical design information of the new or modified library suitably corresponds to each other.

REFERENCES:
patent: 6195786 (2001-02-01), Raghunathan et al.
patent: 6505322 (2003-01-01), Yamashita et al.
patent: 6574779 (2003-06-01), Allen et al.

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