System and method for providing testing and failure analysis...

Details System and method for providing testing and failure analysis... System and method for providing testing and failure analysis...

2007-05-08

2007-05-08

Britt, Cynthia (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S763000

Reexamination Certificate

active

10846004

ABSTRACT:
A system and method is disclosed for testing integrated circuits that contain memory devices. A plurality of test circuits is created in which each test circuit incorporates a physical fault in a memory bit cell. Each of the test circuits generates a distinct electrical signature that is due to presence of the physical fault in the test circuit. The electrical signatures from the test circuits are compared with a signal from an integrated circuit memory device to determine whether any of the physical faults in the test circuits are present in the integrated circuit memory device.

REFERENCES:
patent: 4715034 (1987-12-01), Jacobson
patent: 5491665 (1996-02-01), Sachdev
patent: 6519725 (2003-02-01), Huisman et al.
patent: 2004/0015756 (2004-01-01), Chiu et al.

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