Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2001-07-17
2002-08-20
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S230060
Reexamination Certificate
active
06438046
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to Built-In-Self-Repair (BISR) techniques utilized for testing and repair of high density memory arrays of Intelligent Random Access Memories (IRAM), Dynamic Random Access Memories (DRAM) and the like, and more specifically to a system and method for providing row redundancy for BISR for such high density arrays.
BACKGROUND OF THE INVENTION
Built-In-Self-Repair (BISR) techniques are increasingly being used to test and repair high density memory arrays of Intelligent Random Access Memories (IRAM), Dynamic Random Access Memories (DRAM), and the like. BISR utilizes on-chip circuitry for automatically testing the memory array, and optionally performing a soft-repair of failed elements (rows, columns, I/Os, etc.) of the memory array discovered during test. Without BISR such high density memories would not yield well resulting in increased cost for their manufacture.
BISR uses Built-In-Self-Test (BIST) to test the memory elements and store the address of the defective element (e.g., row, column, input/output (I/O), or the like). BISR then remaps the defective elements using available redundant elements of the memory and stores the repair solution (i.e., the addresses of defective elements and the addresses of redundant elements of the memory array to which the defective elements have been remapped) in soft latches at least during the initial check of the memory. Next, BISR again runs BIST to verify the repair.
Typically, row redundancy schemes employed by BISR utilize a remap circuit that compares the incoming address provided by BIST with the stored defective address. If matched, corresponding redundant row address is activated and the defective row is disabled. Typically, defective rows are disabled using one of two methods. In accordance with the first method, defective rows are disabled “on the fly” (i.e. the regular memory word line is disabled when the redundant row address is activated). However, this method requires that the user address be set well in advance so that the comparison may be performed and the defective row disabled, thereby increasing the address setup time. The second method utilizes latches, or, alternately fuses at each row for disabling the row if it is found to be defective. Defective rows are then disabled at the start of the memory power-up by setting the appropriate latches, or, alternately, blowing the appropriate fuses.
The first method, disabling defective rows on the fly, increases address setup time resulting in an address setup penalty, often of as much as 1 to 2 ns, and is thus generally not acceptable for use in most memory designs. Thus, the second approach, disabling defective rows during memory power-up, is normally preferred since it does not increase address setup time. However, the time required to perform a remap of defective row elements may often increase the access time significantly, resulting in a substantial timing penalty. Moreover, innovations in memory circuit design have shortened memory access times, thus reducing time available in which to perform the remap. Thus, for BISR to perform a remap of defective row elements the following equation (Equation 1) must be satisfied:
CLK_WL
NA
+WL_Dout
NA
=CLK_WLR
RA
+WLR_Dout
RRA
(Equation 1)
where CLK_WL
NA
is the delay from clock activation to the normal word line turning on through normal address, WL_Dout
NA
is the time required for the normal word line to turn on (“ON”) to data out, CLK_WLR
RA
is the delay from clock activation to redundant word line turning on (“ON”), and WLR_Dout
RRA
is the time required for the redundant row to turn on (“ON”) to data out. Because setup of the normal (system) address is performed at the same time as it would be without BISR, the time CLK_WLR
RRA
also includes time required to perform the remap (which depends on remap logic). Thus, the time represented by the right side of Equation 1 (CLK_WLR
RA
+WLR_Dout
RRA
) may be larger then the time represented by the left side (CLK_WL
NA
+WL_Dout
NA
) resulting in an access time penalty.
Consequently, it would be advantageous to provide row redundancy for BISR of high density arrays without a timing penalty.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a system and method for providing row redundancy for BISR of high density memory arrays without a timing penalty by decreasing capacitance of the memory array bitlines at least during accessing of rows of redundant memory of a memory array. In this manner, the amount of time required to access the redundant memory is limited so that no timing penalty is incurred by the memory.
In one embodiment, the memory is comprised of a memory array segregated into a plurality of rows including at least one row of redundant memory accessed by a bitline for transfer of data. A decoupler decouples the redundant memory from regular memory of the memory array shortening the bitline for decreasing capacitance of the bitline at least during accessing of the at least one row of redundant memory thus limiting the amount of time required to access the redundant memory so that no timing penalty is incurred.
In a second embodiment, the memory is comprised of a memory array segregated into a plurality of rows including at least one row of redundant memory accessed by a bitline for transfer of data from regular rows of the memory array. A second bitline is arranged in parallel with the first bitline for accessing rows of the redundant memory. The first bitline is connected to an input/output controller during access of regular memory of the memory array while the second bitline is connected to the input/output controller during access of the at least one row of redundant memory thereby reducing capacitance in both bitlines. In this manner, the amount of time required to access the redundant memory is limited so that no timing penalty is incurred.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate presently preferred embodiments of the invention, and together with the general description given above and the detailed description of the preferred embodiments given below, serve to explain the principles of the invention.
REFERENCES:
patent: 5134584 (1992-07-01), Boler et al.
patent: 5539698 (1996-07-01), Suzuki
patent: 5889712 (1999-03-01), Sugibayashi
patent: 6104648 (2000-08-01), Ooishi
patent: 6246631 (2001-06-01), Park
Auduong Gene N.
Ho Hoai
LSI Logic Corporation
Suiter & Associates PC
LandOfFree
System and method for providing row redundancy with no... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for providing row redundancy with no..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for providing row redundancy with no... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2921343