System and method for providing power managed CML...

Details System and method for providing power managed CML... System and method for providing power managed CML...

2007-05-08

2007-05-08

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S081000, C327S534000

Reexamination Certificate

active

11009494

ABSTRACT:
A system and method is provided for providing power managed common mode logic (CML) transmitters for use with main and auxiliary power sources. Power switch circuitry comprising two PMOS transistors switches the CML transmitter output circuit between a main power source node (VDD) and an auxiliary power source node (TXRAIL). A bias circuit biases the two PMOS transistors to place the main power source voltage on the auxiliary power source node (TXRAIL) when the value of the main power source voltage is nonzero. The bias circuit also biases the two PMOS transistors to remain off when the value of the main power source voltage on the main power source node (VDD) is zero.

REFERENCES:
patent: 5153853 (1992-10-01), Eby et al.
patent: 5559464 (1996-09-01), Orii et al.
patent: 6545525 (2003-04-01), Itoh et al.
patent: 6556071 (2003-04-01), Notani et al.
patent: 6833748 (2004-12-01), Cho
patent: 6954110 (2005-10-01), Li
patent: 2004/0246026 (2004-12-01), Wang et al.

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