Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-26
2009-11-10
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S013000
Reexamination Certificate
active
07617474
ABSTRACT:
Serious defects on a mask can compromise the functionality of the integrated circuits formed on the wafer. Nuisance defects, which do not affect the functionality, waste expensive resources. A defect analysis tool with job-based automation can accurately and efficiently determine defect printability. This tool can run a job, using a mask file, to simulate the wafer exposure that the mask would provide under a given set of parameters. These parameters can relate to the mask itself, the inspection system used to create the mask file, and the stepper that can be used to expose the mask. The processes performed during the job can be done uniformly for defects on the mask. This uniformity allows the tool to efficiently run multiple jobs. The results of the job can be presented using different levels of detail to facilitate user review.
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Chang Fang-Cheng
Pang Linyong
Bever Hoffman & Harms LLP
Harms Jeanette S.
Siek Vuthe
Synopsys Inc.
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