Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-04-18
2004-06-01
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C139S142000, C139S143000
Reexamination Certificate
active
06745296
ABSTRACT:
BACKGROUND
The present invention relates generally to computer systems and methods, and more particularly, to a system and method that provides cacheable SMRAM.
The assignee of the present invention develops firmware for computer systems known as a basic input and output system, or BIOS, along with other firmware and software that is employed in personal computer systems. In certain processors manufactured by Intel, for example, system management mode (SMM) is a special-purpose operating mode that is provided to handle system-wide functions such as power management, system hardware control, or proprietary OEM-designed code.
SMM is intended for use by system firmware, not by applications software or general-purpose systems software. SMM provides a distinct and easily isolated processor environment that operates transparently with respect to the operating system or executive and software applications.
When a processor is executing SMM code, it is said to be in SMM mode. At all other times the processor is executing foreground code in real or protected mode and is said to be in foreground mode.
When SMM is invoked through a system management interrupt (SMI), the current state of the processor (the processor's context) is saved, and the processor switches to SMM in a separate operating environment contained in system management RAM (SMRAM). While in SMM, the processor executes SMI handler code to perform operations such as powering down unused disk drives or monitors, executing proprietary code, or placing the system in a suspended state.
When the SMI handler has completed its operations, it executes a resume instruction. The resume instruction causes the processor to reload its saved context, switch back to foreground mode, and resume execution of foreground code.
The processor handles an SMI on an architecturally defined “interruptible” point in program execution (which is commonly at an Intel Architecture instruction bound-ary). When the processor receives an SMI, it waits for all instructions to retire and for all stores to complete. The processor then saves its current context in SMRAM, enters SMM, and begins to execute the SMI handler.
The only way to exit from SMM is to execute the resume instruction. The resume instruction is only available in SMM. The resume instruction restores the processor's context by loading the state save image from SMRAM back into the processor's registers. It then returns program control back to the interrupted or foreground program code.
In conventional computer systems, executing code above one megabyte of SMRAM with a write-back cache enabled has the potential to destroy the data in SMRAM area and hang the system. This is because cache line fills caused by reads and writes to addresses occupied by the SMRAM area while executing code outside of SMM (in foreground mode) may not actually be written back until a later time when executing code in SMM.
Since reads to these memory locations that are made while executing code outside of SMM fill the cache with unknown data (such as 0xFFFFFFFFh, for example), these values are later written in SMRAM while dispatching an SMI. Also if reads to the memory locations that have the SMI dispatcher codes while executing code outside of SMM fill the cache with some unknown data, the system will hang in SMM as the SMI is generated. This means that a program, driver or virus that reads or writes these addresses could cause the system to fail or hang.
Executing code above one megabyte of SMRAM with the write-back cache disabled is one potential solution that avoids corruption of the data above one megabyte of SMRAM. However, this solution increases the latency of the SMI, which may be more than a maximum acceptable latency of 500 microseconds.
Another option is to not use TSEG/HSEG chipset features and use a portion of system memory as the SMRAM. However, this type of SMRAM area is not secure while operating outside of SMM.
A computer search of the US Patent and Trademark Office patent database was performed which uncovered a number of possible prior art patents. Patents uncovered in the search included U.S. Pat. Nos. 5,544,344, 5,638,532, 5,954,812, 5,596,741, and 5,475,829. A review of these patents reveals that these patents are generally unrelated to the specifics of the present invention.
It is therefore an objective of the present invention to provide a method and apparatus that implement a cacheable above one megabyte SMRAM.
SUMMARY OF THE INVENTION
To accomplish the above and other objectives, the present invention comprises systems and methods that provide for cacheable above one megabyte SMRAM. Exemplary systems and methods comprise a central processing unit (CPU) including a processor (or microprocessor), a system management interrupt (SMI) dispatcher (which is typically part of system firmware or basic input/output system (BIOS)), a level
1
(L
1
) cache, and a level
2
(L
2
) cache. The CPU is coupled by way of the bus interface and a bus to a chipset memory controller that interfaces to a memory. The memory comprises a lower memory (referred to as system memory), an upper memory, and an extended memory containing SMRAM.
The systems and methods provide for cacheable above one megabyte SMRAM as follows. The present invention secures the SMRAM while operating outside of SMM. The present invention gains the benefit of caching by enabling TSEG/HSEG chipset features and performing various caching and un-caching operations. The TSEG/HSEG chipset features function to define the boundaries of the SMRAM.
The present invention sets the SMRAM to be uncacheable while operating outside of SMM. When an SMI is generated, the CPU operation is transferred to the SMM. The SMI dispatcher changes cache settings to cache the extended memory and the SMRAIM with write-through. The SMI dispatcher caches the extended memory with write-back and sets the SMRAM to be uncacheable upon generation of a resume instruction (exit system management interrupt, or exit SMI) which exits the SMM.
In operation, the SMM is invoked by a SMI. The CPU informs the chipset that it is in SMM, and the chipset memory controller opens the SMRAM (including setting an AB segment, along with TSEG and HSEG segments). Thus, the chipset memory controller enables the CPU to access the SMRAM. The CPU saves the current state of the processor to SMRAM.
The CPU executes the SMI dispatcher (or SMI handler). In accordance with the present invention, the SMI dispatcher changes the caching setting as soon as possible to set the extended memory and TSEG/HSEG to be cacheable with write-through. The SMI dispatcher then services the SMI event (i.e., the event that invoked SMI). Then, the SMI dispatcher changes the caching setting to cache the extended memory with write-back and sets the TSEG/HSEG to be uncacheable.
After the SMI handler or dispatcher has completed its operation, it executes a resume (RSM) instruction. This instruction causes the processor to reload the saved context of the CPU, switch back to non-SMM mode. The chipset memory controller is informed that CPU switched back to non-SMM mode, and it closes the SMRAM, so that the CPU cannot access SMRALM.
REFERENCES:
patent: 5544344 (1996-08-01), Frame et al.
patent: 5638532 (1997-06-01), Frame et al.
patent: 6453278 (2002-09-01), Favor et al.
McLean-Mayo Kimberly
Phoenix Technologies Ltd.
LandOfFree
System and method for providing cacheable smram does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System and method for providing cacheable smram, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for providing cacheable smram will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3365708