Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-02-07
2006-02-07
Perveen, Rehana (Department: 2112)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S113000, C710S241000, C711S147000, C711S158000
Reexamination Certificate
active
06996656
ABSTRACT:
A computing system having at least one microprocessor and a memory subsystem coupled to the at least one microprocessor. A memory controller is coupled to manage memory transactions between the memory subsystem and the at least one microprocessor. At least one arbitration port is coupled to the memory controller and configured to receive an external arbitration signal.
REFERENCES:
patent: 4628488 (1986-12-01), Saku et al.
patent: 5230057 (1993-07-01), Shido et al.
patent: 5396602 (1995-03-01), Amini et al.
patent: 5404538 (1995-04-01), Krappweis, Sr.
patent: 5570040 (1996-10-01), Lytle et al.
patent: 5737766 (1998-04-01), Tan
patent: 5892962 (1999-04-01), Cloutier
patent: 5903771 (1999-05-01), Sgro et al.
patent: 5905878 (1999-05-01), LaBerge
patent: 5943483 (1999-08-01), Solomon
patent: 5953743 (1999-09-01), Jeddeloh
patent: 6023755 (2000-02-01), Casselman
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6076152 (2000-06-01), Huppenthal et al.
patent: 6085263 (2000-07-01), Sharma et al.
patent: 6088761 (2000-07-01), Aybay
patent: 6192439 (2001-02-01), Grunewald et al.
patent: 6216191 (2001-04-01), Britton et al.
patent: 6226776 (2001-05-01), Panchul et al.
patent: 6243793 (2001-06-01), Aucsmith et al.
patent: 6314499 (2001-11-01), Kermani
patent: 6330647 (2001-12-01), Jeddeloh et al.
patent: 6415369 (2002-07-01), Chodnekar et al.
patent: 6434687 (2002-08-01), Huppenthal
patent: 6594730 (2003-07-01), Hum et al.
patent: 6654833 (2003-11-01), LaBerge
patent: 6745369 (2004-06-01), May et al.
patent: 6775718 (2004-08-01), Saruwatari et al.
patent: 6820142 (2004-11-01), Hofstee et al.
patent: 2001/0042178 (2001-11-01), Achilles et al.
patent: 2002/0120709 (2002-08-01), Chow et al.
patent: 2003/0061453 (2003-03-01), Cosky et al.
patent: 2003/0101307 (2003-05-01), Gemelli et al.
patent: 2003/0185032 (2003-10-01), Zagorianakos et al.
Agarwal, A., et al., “The Raw Compiler Project”, pp. 1-12, http://caq-www.lcs.mit.edu/raw, Proceedings of the Second SUIF Compiler W rkshop, Aug. 21-23, 1997.
Albaharna, Osama, et al., “On the Viability f FPGA-based integrated coprocessors”, © 1996 IEEE, Publ. No. 0-8186-7548-Sep. 1996, pp. 206-215.
Amerson, Rick, et al., “Teramac—Configurable Custom Computing”, © 1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 32-38.
Barthel, Dominique Aug. 25-26, 1997, “PVP a Parallel Vide coProcessor”, Hot Chips IX, pp. 203-210.
Bertin, Patrice, et al., “Programmable active memories: a perf rmanc assessment”, © 1993 Massachusetts Institute of Technology, pp. 88-102.
Bittner, Ray, et al., “Computing kernels implemented with a wormhole RTR CCM”, © 1997 IEEE, Publ. No. 0-8186-8159-Apr. 1997, pp. 98-105.
Buell, D., et al. “Splash 2: FPGAs in a Custom Computing Machine—Chapter1—Custom Computing Machines: An Introduction”, pp. 1-11, http://www.computer.org/espress/catalog/bp07413/spls-ch1.html (originally believed published in J. of Supercomputing, vol. IX, 1995, pp. 219-230.
Casselman, Steven, “Virtual Computing and The Virtual Computer”, © 1993 IEEE, Publ. No. 0-8186-3890-Jul. 1993, pp. 43-48.
Chan, Pak, et al., “Architectural tradeoffs in field-programmable-device-based computing systems”, © 1993 IEEE, Publ. No. 0-8186-3890-Jul. 1993, pp. 152-161.
Clark, David, et al., “Supporting FPGA microprocessors through retargetable software tools”, © 1996 IEEE, Publ. No. 0-8186-7548-Sep. 1996, pp. 195-103.
Cuccaro, Steven, et al., “The CM-2X: a hybrid CM-2/Xilink prototype”, © 1993 IEEE, Publ. No. 0-8186-3890-Jul. 1993, pp. 121-130.
Culbertson, W. Bruce, et al., “Exploring architectures for volume visualization on the Teramac custom computer”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 80-88.
Culbertson, W. Bruce, et al., “Defect tolerance on the Teramac custom computer”, © 1997 IEEE, Publ. No. 0-8186-8159-4/97. pp. 116-123.
Dehon, Andre, “DPGA-Coupled microprocessors: commodity IC for the early 21stcentury”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 31-39.
Dehon, A., et al., “Matrix A Reconfigurable Computing Device with Configurable Instruction Distribution”, Hot Chips IX, Aug. 25-26, 1997, Stanford, California, MIT Artificial Intelligence Laboratory.
Dhaussy, Philippe, et al., “Global control synthesis for an MIMD/FPGA machine”, © 1994 IEEE, Publ. No. 0-8186-5490-2/94, pp. 72-81.
Elliott, Duncan, et al., “Computational Ram: a memory-SIMD hybrid and its application to DSP”, © 1992, IEEE, Publ. No. 0-7803-0246-X/92, pp. 30.6.1-30.6.4.
Fortes, Jose, et al., “Systolic arrays, a survey of seven projects”, © 1987 IEEE, Publ. No. 0018-9162/87/0700-0091, pp. 91-103.
Gokhale, M., et al., “Processing in Memory: The Terasys Massively Parallel PIM Array” © Apr. 1995, IEEE, pp. 23-31.
Gunther, Bernard, et al., “Assessing Document Relevance with Run-Time Reconfigurable Machines”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 10-17.
Hagiwara, Hiroshi, et al., “A dynamically microprogrammable computer with low-level parallelism”, © 1980 IEEE, Publ. No. 0018-9340/80/07000-0577, pp. 577-594.
Hartenstein, R. W., et al. “A General Approach in System Design Integrating Reconfigurable Accelerators,” http://xputers.informatik.uni-kl.de/papers/paper026-1.html, IEEE 1996 Conference, Austin, TX, Oct. 9-11,.
Hartenstein, Reiner, et al., “a reconfigurable data-driven ALU for Xputers”, © 1994, IEEE, Publ. No. 0-8186-5490-2/94, pp. 139-146.
Hauser, John, et al.: “GARP: a MIPS processor with a reconfigurable co-processor”, © 1997 IEEE, Publ. No. 0-08186-8159-4/97, pp. 12-21.
Hayes, John, et al., “A microprocessor-based hypercube, supercomputer”, © 1996 IEEE, Publ. No. 0272-1732/86/1000-0006, pp. 6-17.
Herpel, H.-J., et al., “A Reconfigurable Computer for Embedded Contr l Applications”, © 1993 IEEE, Publ. No. 0-8186-3890-7/93, pp. 111-120.
Hogl, H., t al., “Enable++: A second generation FPGA processor”, © 1995 IEEE, Publ. No. 0-8186-7086-X/95, pp. 45-53.
King, William, et al., “Using MORRPH in an industrial machine vision system”, © 1996 IEEE, Publ. No. 08186-7548-9/96, pp. 18-26.
Manohar, Swaminathan, et al., “A pragmatic approach to systolic design”, © 1988 IEEE, Publ. No. CH2603-9/88/0000/0463. pp. 463-472.
Mauduit, Nicolas, et al., “Lneuro 1.0: a piece of hardware LEGO for building neural network systems,” © 1992 IEEE, Publ. No. 1045-9227/92, pp. 414-422.
Mirsky, Ethan A., “Coarse-Grain Reconfigurable Computing”, Massachusetts Institute of Technology, Jun. 1996.
Mirsky, Ethan, et al., “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 157-166.
Morley, Robert E., Jr., et al., “A Massively Parallel Systolic Array Processor System”, © 1988 IEEE, Publ. No. CH2603-9/88/0000/0217, pp. 217-225.
Patterson, David, et al., “A case for Intelligent DRAM: IRAM”, Hot Chips VIII, Aug. 19-20, 1996, pp. 75-94.
Peterson, Janes, et al., “Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures”, © 1996 IEEE, Publ. No. 0-8186-7548-9/96, pp. 178-187.
Schmit, Herman, “Incremental reconfiguration for pipelined applications,” © 1997 IEEE, Publ. No. 0-8186-8159-4/97, pp. 47-55.
Sitkoff, Nathan, et al., “Implementing a Genetic Algorithm on a Parallel Custom Computing Machine”, Publ. No. 0-8186-7086-X/95, pp. 180-187.
Stone, Harold, “A logic-in-memory computer”, © 1970 IEEE, IEEE Transactions on Computers, pp. 73-78, Jan. 1990.
Tangen, Uwe, et al., “A parallel hardware evolvable computer POLYP extended
Hogan & Hartson LLP
Kubida William J.
Langley Stuart T.
Lee Christopher E.
Perveen Rehana
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