System and method for providing adjustable read margins in a...

Details System and method for providing adjustable read margins in a... System and method for providing adjustable read margins in a...

2006-09-21

2008-11-25

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S733000

Reexamination Certificate

active

07458005

ABSTRACT:
A system and method for effectuating a self-timed clock (STC) loop for memory access operations. In one embodiment, the method includes configuring a particular access margin value setting based on configuration data of at least one memory instance of a memory device; and applying the particular access margin value setting to a reference cell assembly associated with the at least one memory instance for facilitating generation of a self-timed clock signal that is optimized for the at least one memory instance.

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Kim et al., Built in self repair for embedded high density SRAM, IEEE International Test Conference, Oct. 1998, pp. 1112-1119.

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