System and method for providing a fast and efficient comparison

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

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Details

714752, 714755, 714757, 711114, 711112, G06F 1200, G06F 500, G06F 900, G06F 1100

Patent

active

060618221

ABSTRACT:
An IDE controller having an IDE interface that includes a primary channel for transmitting primary data from a primary device and a secondary channel for transmitting secondary data from a secondary device; a primary CRC circuit for receiving the primary data, performing an operation on the primary data and generating primary CRC values; a secondary CRC circuit for receiving the secondary data, performing an operation on the secondary data and generating secondary CRC values, wherein the primary data and the secondary data are transmitted to their respective CRC circuits concurrently; and a compare circuit for comparing the primary CRC values with the secondary CRC values and generating compare values.

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