System and method for providing a clock and data recovery...

Details System and method for providing a clock and data recovery... System and method for providing a clock and data recovery...

2004-10-26

2009-08-04

Lamarre, Guy J (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error count or rate

Reexamination Certificate

active

07571360

ABSTRACT:
A system and method is disclosed for providing a clock and data recovery circuit with a fast bit error rate self test capability. A bit error rate test control unit is provided that causes the clock and data recovery circuit to sample data adjacent to an edge of a bit period to create errors at a relatively high bit error rate. This is accomplished by intentionally introducing an interpolator offset in a phase position of a data clock signal. The test control unit generates a first bit error rate and then subsequently generates a second bit error rate. The test control unit then uses the values of the first and second bit error rates to extrapolate a value of bit error rate for the clock and data recovery circuit that corresponds to a zero value of interpolator offset.

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