Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-07-22
2001-02-20
Nguyen, Hiep T. (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S185190, C365S185220
Reexamination Certificate
active
06192445
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to systems and methods for programming the memory cells of programmable memory devices, and in particular, to systems and methods for programming EPROM cells which require that multiple programming pulses be applied to selected memory cells.
2. Description of the Related Art
Referring to
FIG. 1
, as is well known in the art, the transistor forming a memory cell for an electrically programmable read only memory device (EPROM) has a floating polysilicon gate which is located between an access gate and the substrate and is electrically isolated from the substrate by a gate oxide and from the access gate by a dielectric inter-poly oxide.
During programming, a high programming voltage VPP is applied to the access gate while a lower voltage VD is applied to the drain and the source is grounded. As electrons flow from the source to the drain, they pick up kinetic energy and their path is altered by an electric field which is between the access gate and substrate and is generated by the potential difference between the programming voltage VPP on the access gate and the biasing voltage VD on the drain. Those electrons which achieve sufficient kinetic energy accelerate vertically toward the floating gate, passing through the gate oxide, and are trapped on the floating gate electrode, thereby creating a net negative voltage on the floating gate which opposes any electric field created by a positive voltage on the access gate. This results in a substantial increase in the threshold voltage required to transform the EPROM memory cell from a nonconductive state to a conductive state.
With conventional EPROM programming techniques, a small number of sample EPROM cells are used to sample the programmability of the remaining cells. Each sample cell is programmed by applying a sample programming pulse with a known relatively short pulse width and is immediately verified. If needed, more pulses of the same short width are applied followed by further verification until such cell is fully programmed. The maximum number of such short pulses that any of the sample cells took to reach the desired programming state is then used to establish the width, i.e., duration, of a longer programming pulse that will then be applied to the remaining cells. Typically, the duration of this longer pulse is simply set equal to the combined durations of the short pulses that were used to program the slowest sample cell. Thereafter, all remaining cells are then programmed by applying one or more of such longer pulses, as required, to each cell.
Such conventional technique, however, generally results in a significant amount of wasted time in programming and verifying an EPROM device. For example, for each cell which requires multiple programming pulses, the duration of each one of such programming pulses is that of the longest programming pulse duration found necessary to program the slowest sample memory cell. However, if the cell currently being programmed is not as slow as the slowest sample cell, but requires multiple programming pulses nonetheless, a proportionately significant amount of time can be wasted by applying extra programming pulses which are longer than necessary.
Accordingly, it would be desirable to have a programming technique in which advantage can be taken of the fact that it is statistically unlikely that most memory cells which are slower to program than the slowest sample memory cell will have programming times which are integer multiples of the programming time of the slowest sample cell.
SUMMARY OF THE INVENTION
A programming system and method in accordance with the present invention provides for the programming of programmable memory devices in significantly less time than conventional techniques. Each memory cell is programmed by using an initial programming pulse having a duration which is based upon programming tests conducted upon sample memory cells and then supplementing such initial programming with auxiliary programming pulses, as needed, each of which has a duration which is shorter than the initial programming pulse duration.
In accordance with one embodiment of the present invention, a programming system for programming a programmable memory device having multiple individually programmable memory cells includes a programming signal source and a programming controller. The programming signal source is configured to couple to a programmable memory device which includes multiple programmable sample memory cells and multiple programmable main array memory cells and provide thereto multiple programming signals by performing the steps of:
(a) receiving a programming mode control signal and in accordance therewith applying a programming mode signal to the programmable memory device in accordance with which the programmable memory device becomes configured for programming;
(b) receiving a plurality of sample programming control signals and in accordance therewith applying a plurality of sample programming signals to the programmable memory device;
(c) receiving a sample programming pulse control signal and in accordance therewith applying a sample programming pulse having a sample programming pulse duration to one of the plurality of programmable sample memory cells;
(d) receiving a programming verification control signal and in accordance therewith applying a programming verification signal to the programmable memory device;
(e) receiving a plurality of main array programming control signals and in accordance therewith applying a plurality of main array programming signals to the programmable memory device;
(f) receiving an initial main array programming pulse control signal and in accordance therewith applying an initial main array programming pulse having an initial main array programming pulse duration to one of the plurality of programmable main array memory cells;
(g) receiving an auxiliary main array programming pulse control signal and in accordance therewith applying an auxiliary main array programming pulse having an auxiliary main array programming pulse duration to the one of the plurality of programmable main array memory cells.
The programming controller is coupled to the programming signal source and is configured to couple to the programmable memory device and perform the steps of:
(h) providing the programming mode control signal;
(i) providing the plurality of sample programming control signals;
(j) providing the sample programming pulse control signal;
(k) providing the programming verification control signal;
(l) receiving from the programmable memory device, in response to the programming verification signal, a sample programming state signal which represents a programming state of the one of the plurality of programmable sample memory cells;
(m) comparing the programming state of the one of the plurality of programmable sample memory cells to a sample reference state;
(n) repeating steps (h), (i), (j), (k) and (l) if the programming state of the one of the plurality of programmable sample memory cells does not transcend the sample reference state, otherwise proceeding to step (o);
(o) determining a combination of the sample programming pulse durations of the sample programming pulses applied by the programming signal source in step (c) in accordance with steps (h), (i), (j), (k), (l), (m) and (n);
(p) repeating steps (h), (i), (j), (k), (l), (m), (n) and (o) for each remaining one of the plurality of programmable sample memory cells, then proceeding to step (q);
(q) establishing the initial main array programming pulse duration to be approximately equal to a selected one of the combinations of the sample programming pulse durations as determined in accordance with steps (h), (i), (j), (k), (l), (m), (n), (o) and (p);
(r) establishing the auxiliary main array programming pulse duration to be shorter than the initial main array programming pulse duration;
(s) providing the plurality of main array programming control signals;
(t) providing the initial main array programming pulse contro
Altera Corporation
Limbach & Limbach L.L.P.
Nguyen Hiep T.
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