Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-02-06
2007-02-06
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S002000
Reexamination Certificate
active
11078630
ABSTRACT:
A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.
REFERENCES:
patent: 3751647 (1973-08-01), Maeder et al.
patent: 4795964 (1989-01-01), Mahant-Shetti et al.
patent: 4835466 (1989-05-01), Maly et al.
patent: 4939681 (1990-07-01), Yokomizo et al.
patent: 5067101 (1991-11-01), Kunikiyo et al.
patent: 5068547 (1991-11-01), Gascoyne
patent: 5070469 (1991-12-01), Kunikiyo et al.
patent: 5286656 (1994-02-01), Keown et al.
patent: 5301118 (1994-04-01), Heck et al.
patent: 5438527 (1995-08-01), Feldbaumer et al.
patent: 5448476 (1995-09-01), Kurokawa et al.
patent: 5486786 (1996-01-01), Lee
patent: 5497381 (1996-03-01), O'Donoghue et al.
patent: 5502643 (1996-03-01), Fujinaga
patent: 5625268 (1997-04-01), Miyanari
patent: 5627083 (1997-05-01), Tounai
patent: 5629877 (1997-05-01), Tamegaya
patent: 5655110 (1997-08-01), Krivokapic et al.
patent: 5703381 (1997-12-01), Iwasa et al.
patent: 5767542 (1998-06-01), Nakamura
patent: 5773315 (1998-06-01), Jarvis
patent: 5778202 (1998-07-01), Kuroishi et al.
patent: 5790479 (1998-08-01), Conn
patent: 5798649 (1998-08-01), Smayling et al.
patent: 5822258 (1998-10-01), Casper
patent: 5852581 (1998-12-01), Beffa et al.
patent: 5867033 (1999-02-01), Sporck et al.
patent: 5903012 (1999-05-01), Boerstler
patent: 5966527 (1999-10-01), Krivokapic et al.
patent: 5982929 (1999-11-01), Ilan et al.
patent: 6005829 (1999-12-01), Conn
patent: 6063132 (2000-05-01), DeCamp et al.
patent: 6066179 (2000-05-01), Allan
patent: 6072804 (2000-06-01), Beyers, Jr.
patent: 6075417 (2000-06-01), Cheek et al.
patent: 6075418 (2000-06-01), Kingsley et al.
patent: 6118137 (2000-09-01), Fulford et al.
patent: 6124143 (2000-09-01), Sugasawara
patent: 6134191 (2000-10-01), Alfke
patent: 6184048 (2001-02-01), Ramon
patent: 6289257 (2001-09-01), Sekine
patent: 6393602 (2002-05-01), Atchison et al.
patent: 1097829 (1995-01-01), None
Guldi et al., “Analysis and Modeling of Systematic and Defect Related Yield Issues During Early Development of New Technology,” 1998 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 7-12.
Nemoto et al., “A New Systematic Yield Ramp Methodology,” 1999 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 21-24.
Wong et al., “Micro Yield Modeling for IC Processes,” 1995 IEEE Region 10, Int's Conference on Microelectronics and VLSI, pp. 230-233.
Wong et al., “A Statistical Parametric and Probe Yield Analysis Methodology,” 1996 IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 131-139.
Wong et al., “A Systematic Approach to Identify Critical Yield Sensitive Parametric Parameters,” 1997 2nd Int'l Workshop on Statistical Metrology, pp. 56-61.
Wong et al., “A Statistical Approach to Identify Semiconductor Process Equipment Related Yield Problems,” 1997 IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 69-73.
Wong et al., “Development of new methodology and technique to accelerate region yield improvement,” IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp. 82-85.
Khare et al., “Extraction of Defect Characteristics for Yield Estimation Using the Double Bridge Test Structure,” 1991 VLSITSA, pp. 428-432.
Khare et al., “Yield Oriented CAD Defect Diagnosis,” 1995 IEEE Trans. of Semiconductor Manufacturing, pp. 195-206.
Nurani et al., “In-Line Yield Predictoin Methodologies Using Patterned Wafer Inspection Information,” 1998 IEEE Trans. on Semiconductor Manufacturing.
Khare et al., “Extraction of Defect Characteristics for Yield Estimation Using the Double Bridge Test Structure,” 1991 IEEE, pp. 428-432.
Yun et al., “Evaluating the Manufacturability of FaAS/AIGaAs Multiple Quantum Well Avalanche Photodiodes Using Neural Networks,” 1997 IEEE, pp. 105-112.
Hansen et al., “Effectiveness of Yield-Estimation and Reliability-Prediction Based on Wafer Test Chip Measurements,” 1997 IEEE, pp. 142-148.
Walton et al., “A Novel Approach for Reducing the Area Occupied by Contact Pads on Process Control Chips,” 1990 IEEE Int'l Conference on Microelectronic Test Structures, pp. 75-80.
Beckers et al., “The Spidermarks: A New Approach for Yield Monitoring Using Product Adaptable Test Structures,” 1990 IEEE Int'l Conference on Microelectronic Test Structures, pp. 61-66.
Liebman et al., “Understanding Across Chip Line Width Variation: The First Step Toward OPC,” SPIE vol. 3051, pp. 124-136.
To et al., “Mismatch Modeling and Characterization of Bipolar Transistors for Statistical CAD,” 1996 IEEE Trans. on Circuits and Systems—I: Fundamental Theory and Applications, pp. 608-610.
Conti et al., “Parametric Yield Formulation of MOS IC's Affected by Mismatch Effect,” 1999 IEEE Trans. on CAD of ICs and Systems, pp. 582-596.
Michael et al., “A Flexible Statistical Model for CAD of Submicrometer Analog CMOS ICs,” 1993 IEEE/ACM Int'l Conference on CAD, pp. 330-333.
Felt et al., “Measurement and Modeling of MOS Transistor Current Mismatch in Analog ICs,” 1994 IEEE/ACM Int'l Conference on CAD, pp. 272-277.
Ogrenci et al., “Incorporating MOS Transistor Mismatches into Training of Analog Nerual Networks,” 1998 Proc. of NC Int'l ICSC/IFAC Symposium on Neural Computation,no page numbers.
Hansen et al., “Effectiveness of Yield-Estimation and Reliability-Prediction Based on Wafer Test Chip Measurements,” 1997 IEEE, pp. 142-148.
Walton et al., “A Novel Approach for Reducing the Area Occupied by Contact Pads on Process Control Chips,” 1990 IEEE Int'l Conference on Microelectronic Test Structures, pp. 75-80.
Beckers et al., “The Spidermarks: A New Approach for Yield Monitoring Using Product Adaptable Test Structures,” pp. 61-66.
Liebman et al., “Understanding Across Chip Line Width Variation: The First Step Toward OPC,” SPIE vol. 3051, pp. 124-136, no date.
Henry, Todd (Sep. 8, 1999) “Application of ADC Techniques to Characterize Yield-Limiting Defects Identified with the Overlay of E-Test/Inspection Data on Short Loop Process Testers,” Advanced Semiconductor Manufacturing Conference and Workshop, 1999 IEEE/SEMI, Boston, MA, Sep. 8-10, 1999, pp. 330-337.
Hsieh, Sunnys et al. (Oct. 11, 1999) “Novel Assessment of Process Control Monitor in Advanced Semiconductor Manufacturing: A Complete Set of Addressable Failure Site Test Structures (AFS-TS),” Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on, Santa Clara, CA, Oct. 11-13, 1999, pp. 241-244.
Milor, Linda et al. (Oct. 11, 1999) “Layer Yield Estimation Based on Critical Area and Electrical Defect Monitor Data,” Semiconductor Manufacturing Conference Proceedings, 1999 IEEE International Symposium on, Santa Clara, CA, Oct. 11-13, 1999, pp. 99-0102.
Ciplickas Dennis J.
Davis Joseph C.
Hess Christopher
Kibarian John
Lee Sherry F.
Garbowski Leigh M.
Morrison & Foerster / LLP
PDF Solutions, Inc.
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