Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1997-07-09
1999-08-03
Cabeca, John W.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711158, 711159, G06F 1500
Patent
active
059338563
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a system and a method respectively for processing of memory data. The invention also relates to a communications system comprising such a system for processing of memory data.
Memory communication for stored data variables within a data processing system often consumes a great part of the capacity that is available within the data communication unit for intercommunication between the location for storing the variables and the unit for data processing.
It is common that a number of variables share the memory area of a word. Variables sharing the memory area of a word is efficient from a memory packing point of view. Among others such sharing may contribute in reducing the number of memory accesses. In spite thereof, however, the available capacity is sometimes not used in an efficient way.
For example in large systems processing data in real time which require very much memory it is particularly important to have an organisation of the memory so that a high storing and communication capacity can be provided.
STATE OF ART
Many different alternatives have been suggested for how to, in an efficient way, use the capacity for storing and communication between the location for storing of variables and that or those units which are to process data. It is a problem that the memories are comparatively slow as compared to the data processing units from an internal point of view. With the known solutions to these problems it has been intended to achieve an efficient usage of memory accesses.
In U.S. Pat. No. 4,354,231 cache-technique is used. The cache-technique is based on storing memory data that is often addressed in a fast memory, a so called cache-memory which is controlled by various algorithms. Therefor memory operations directed towards a slow memory are often handled by the cache-memory which has an access time which is considerably shorter. According to U.S. Pat. No. 4,354,231 an address calculation is initiated in good time before the relevant program instructions are to be executed in order to reduce the waiting time. The arrangement according to the above mentioned US-document for reducing the time for instruction execution comprises a buffer memory in which instructions read from the program memory are sequentially and temporarily stored in an execution buffer. The execution buffer is provided with instructions of different kinds, of which a first kind relates to writing or reading in the data memory and a second kind of instructions places address parameters in a register memory. First and second activation means which are intended for initiation-transfer of address parameters from the register memory to the address processing means for modifying the address when an indication is present in a registering means and the instruction is in turn to be handled and is of the above mentioned first kind, or for removing the indication from the registration means after the transmission has been effected and the second activation means which are connected to the address handling means, respectively respond to a base address read out from a reference memory to the address handling means for initiation of a calculation of the absolute address when at the same time none of the ahead stored instructions are of the second kind, i.e. the kind which places the address parameters in the register memory etc. Thus a certain time saving is provided thereby through an efficient usage of the time. However, except for the time savings, which even may be minor, memory data of a system can be localized in such a way that the application of the cache-technique indeed does not give the desired result and may in fact be inefficient.
Furthermore, the cache-technique is not efficient for randomly occurring data accesses.
EP-A-0 439 025 discloses a data processor having a deferred cache load which comprises an instruction prefetch unit, a memory, a processor bus and a function unit wherein the latter converts logical addresses and provides for storing of preceding memory accesses in
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Avsan Oleg
Wildling Klaus
Cabeca John W.
Telefonaktiebolaget LM Ericsson
Tzeng Fred F.
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