Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-10-24
2006-10-24
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S756000, C714S769000
Reexamination Certificate
active
07127657
ABSTRACT:
A CD-ROM decoder for processing digital data while buffering the digital data in a buffer RAM. The CD-ROM decoder includes a host interface for storing the digital data in the buffer RAM. An EDC processing circuit generates an error detection code using the digital data read from the buffer RAM in a block unit. An ECC processing circuit generates an error correction code with the digital data and the error detection code. An internal RAM stores the digital data and adds the error detection code and the error correction code to the digital data when storing the digital data. A digital signal processor outputs the digital data, the error detection code, and the error correction code that are stored in the internal RAM in a block unit.
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Lee, P.; Chang, S.; Parallel error-trapping and error-detection decoding; Signals, Systems and Computers, 1991. 1991 Conference Record of the Twenty-Fifth Asilomar Conference on□□Nov. 4-6, 1991 pp. 35-38 vol.
Tsukamizu Yuuichiro
Watanabe Tomofumi
Dildine R. Stephen
Fish & Richardson P.C.
Sanyo Electric Co,. Ltd.
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