Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2002-11-27
2004-09-07
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S189011
Reexamination Certificate
active
06788585
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of data processing and more particularly to a system and method for processing data in a memory array.
BACKGROUND OF THE INVENTION
Data processing architectures have grown increasingly complex in data communication and data processing systems. Some data processing systems may include one or more elements that are configured to provide some result or to produce a selected output based on an assigned task. A processor may be generally used to execute one or more tasks in combination with some data storage element that maintains data or information in an integrated circuit environment.
One drawback associated with some data processing architectures is that they suffer from slow processing speeds For example, in pipelined applications, a speed limiting path may be created by components or elements that experience some delay in receiving a requisite input. This may be the result of one or more elements in a system architecture that are unable to process information properly in order to produce a resultant to be communicated to a receiving element or component that relies on that information to execute its assigned task. Thus, a deficiency in one or more elements within an integrated circuit may cause additional components or elements to similarly suffer in performance or efficacy.
Components or elements that wait for some resultant value to be received before proceeding to a next step in a processing operation may inhibit system performance and contribute to inferior processing speeds. Accordingly, the ability to provide a fast and accurate data processing system that allows for resultant values to be seamlessly communicated between components without delay is a significant challenge to system designers and manufacturers of data processing architectures.
SUMMARY OF THE INVENTION
From the foregoing, it may be appreciated by those skilled in the art that a need has arisen for an improved approach for communicating information in a data processing environment. In accordance with one embodiment of the present invention, a system and method for processing data in a memory array are provided that substantially eliminate or greatly reduce disadvantages and problems associated with conventional data processing techniques.
According to one embodiment of the present invention, there is provided a method for processing data that includes receiving a first request in a first clock cycle from a processor for access to a first data segment corresponding to a first address included in the first request. The method also includes receiving a second request in a second clock cycle for access to a second data segment corresponding to a second address included in the second request. The second data segment is disabled from being communicated to the processor and the first data segment is communicated to the processor in response to the second request.
Certain embodiments of the present invention may provide a number of technical advantages. For example, according to one embodiment of the present invention, an approach for processing data in a memory, array is provided that offers enhanced processing speeds. The enhanced processing speed is a result of allowing a read enable that is provided to the memory array to arrive late. When the read enable is inactive, it operates to inhibit data from being communicated from the memory array for a selected clock cycle. Thus, one address may be accessed and read by the memory array but the corresponding data for that address may not be communicated or propagate from the memory array. Instead, the data read during a previous cycle from the memory array will continue to propagate to a processor.
This configuration ensures the accuracy of the data in allowing selected information to be retained and communicated during a designated clock cycle. Thus, selected information may propagate consistently and accurately to a corresponding processor that seeks data from the memory array. This accessing or synchronization protocol further allows multiple components to have access to the memory array without compromising the integrity of the data read from the memory array. Embodiments of the present invention may enjoy some, all, or none of these advantages. Other technical advantages may be readily apparent to one skilled in the art from the following figures, description, and claims.
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Eitrheim John K.
Huxel Jeffrey A.
Baker & Botts L.L.P.
Cisco Technology Inc.
Phung Anh
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